Patent
Method for fabricating capacitor structures using the first contact metal
Efraim Aloni,Yakov Roizin,Alexey Heiman,M. Lisiansky,Amos Fenigstein,Myriam Buchbinder +5 more
- 19 Mar 2008
12
TL;DR: In this article, a capacitor structure is fabricated with only slight modifications to a conventional single-poly CMOS process, and a dielectric layer is formed over the exposed polysilicon structures, which may be salicided or non-salicided.
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Abstract: A capacitor structure is fabricated with only slight modifications to a conventional single-poly CMOS process. After front-end processing is completed, grooves are etched through the pre-metal dielectric layer to expose polysilicon structures, which may be salicided or non-salicided. A dielectric layer is formed over the exposed polysilicon structures. A conventional contact process module is then used to form contact openings through the pre-metal dielectric layer. The mask used to form the contact openings is then removed, and conventional contact metal deposition steps are performed, thereby simultaneously filling the contact openings and the grooves with the contact (electrode) metal stack. A planarization step removes the upper portion of the metal stack, thereby leaving metal contacts in the contact openings, and metal electrodes in the grooves. The metal electrodes may form, for example, transistor gates, EEPROM control gates or capacitor plates.
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Citations
A New 2T Contact Coupling Gate MTP Memory in Fully CMOS Compatible Process
Chiu-Wang Lien,Haw-Yun Wu,Cheng-Wei Tsai,Chen-Mei Huang,Yue-Der Chih,Te-Liang Lee,Chrong Jung Lin +6 more
TL;DR: A new fully logic process compatible 2T multitime programmable (MTP) memory cell has been introduced for embedded logic nonvolatile memory (NVM) applications and adopts a novel contact coupling gate structure as an additional control gate for highly efficient operation and high-density memory applications.
13
Patent
Capacitor using middle of line (mol) conductive layers
PR Chidambaram,Bin Yang +1 more
- 21 Nov 2013
TL;DR: In this paper, a method for fabricating a metal-insulator-metal (MIM) capacito includes depositing a first middle of line (MOL) conductive layer over a shallow trench isolation (STI) region of a semiconductor substrate.
11
Patent
Electronic device including a resistor-capacitor filter and a process of forming the same
Fabio Duarte de Martin,Fabio De Lacerda,Alfredo Olmos +2 more
- 05 Jun 2008
TL;DR: In this article, a low-pass filter and a transistor structure are used to form an electronic device, such as an n-channel transistor or a p-channel transistors, where the input and output terminals are spaced apart from each other and are connected to different components within the electronic device.
7
Patent
Non-volatile split gate memory cells with integrated high k metal gate, and method of making same
Zhou Feng,Liu Xian,Jeng-Wei Yang,Chien-Sheng Su,Nhan Do +4 more
- 01 Aug 2016
TL;DR: In this paper, a method of forming a pair of memory cells that includes forming a polysilicon layer over and insulated from a semiconductor substrate, forming an HKMG layer on the structure and removing portions thereof between the control gates, forming a source region in the substrate adjacent the inner side surfaces of the control gate and forming a conductive erase gate over and insulation from the source region, forming conductive word line gates laterally adjacent to the control gates, and forming drain regions adjacent the word line gates.
6
Patent
Method for manufacturing a finger trench capacitor with a split-gate flash memory cell
Harry-Hak-Lay Chuang,Yu-Hsiung Wang,Chen-Chin Liu +2 more
- 25 Jun 2015
TL;DR: In this article, a split-gate flash memory cell and the resulting integrated circuit are provided, where opants are implanted into regions of the semiconductor substrate lining the one or more trenches.
4
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Patent
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Low contact resistance CMOS circuits and methods for their fabrication
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TL;DR: In this article, a low contact resistance CMOS integrated circuit and method for its fabrication are provided, which consists of a first transition metal electrically coupled to the N-type circuit regions and a second transition metal different than the first to the P type circuit regions.
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Patent
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Yakov Roizin
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TL;DR: In this article, a complimentary nonvolatile memory (CNVM) cell includes an n-channel transistor and a p-channel transistor that have drains connected like a CMOS inverter, and that are controlled by a shared floating gate and a shared control gate.
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Patent
Strained channel CMOS device with fully silicided gate electrode
Bor-Wen Chan,Yuan-Hung Chiu,Han-Jan Tao +2 more
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TL;DR: In this paper, a strained channel NMOS and PMOS device pair including fully silicided gate electrodes and a method for forming the same, the method including providing a semiconductor substrate including NMOS/PMOS device regions including respective gate structures including polysilicon gate electrodes.
37
Patent
Capacitor that includes high permittivity capacitor dielectric
Yee-Chia Yeo,Chenming Hu +1 more
- 13 Jan 2006
TL;DR: In this article, a decoupling capacitor is formed on a semiconductor substrate that includes a silicon surface layer, and a substantially flat bottom electrode is formed in a portion of the semiconductor surface layer.
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