Patent
Method for design optimization using logical and physical information
Douglas B. Boyle,James S. Koford +1 more
- 06 Mar 2001
314
TL;DR: In this paper, a method for design optimization using logical and physical information is provided, which includes a behavioral description of an integrated circuit or a portion of an Integrated Circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements.
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Abstract: A method for design optimization using logical and physical information is provided. In one embodiment, a method for design optimization using logical and physical information, includes receiving a behavioral description of an integrated circuit or a portion of an integrated circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements in accordance with a second cost function, in which the optimizing placement of the circuit elements and the optimizing logic of the circuit elements are performed concurrently. The method can further include optimizing routing in accordance with a third cost function, in which the optimizing routing, the optimizing placement of the circuit elements, and the optimizing logic of the circuit elements are performed concurrently.
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Citations
Patent
Method of optimizing customizable filler cells in an integrated circuit physical design process
Steven E. Charlebois,Paul E. Dunn,George Wilson Rohrbaugh +2 more
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TL;DR: In this article, a filler cell placement algorithm was proposed to optimize the placement of the filler cells in an integrated circuit physical design process, and a method of optimizing the locations, number, and distribution of the customizable filler cells was provided.
198
Patent
Methods and apparatuses for designing integrated circuits
Kenneth S. McElvain,Robert Erickson +1 more
- 05 Dec 2002
TL;DR: In this article, a hardware description language (HDL) code is compiled to produce a technology independent RTL (register transfer level) netlist, and a portion of an area of the IC is allocated to a specific portion of the RTL netlist.
146
Patent
Representing the design of a sub-module in a hierarchical integrated circuit design and analysis system
Michael A. Riepe,Robert M. Swanson,Timothy M. Burks,Lukas P. P. P. van Ginneken,Karen Vahtra,Hamid Savoj +5 more
- 10 Jun 2002
TL;DR: A method for modeling integrated circuit designs in a hierarchical design automation system which utilizes a block abstraction including a set of all database objects (cells, nets, wires, vias, and blockages) that are necessary to achieve accurate placement, routing, extraction, simulation, and verification of the block's ancestors in the hierarchy is presented in this article.
139
Patent
Method and apparatus for automated circuit design
Champaka Ramachandran,Andrew Crews,Kenneth S. Mcelvain +2 more
- 28 May 2004
TL;DR: In this article, the authors present a method to modify a first circuit design to reduce the likelihood of a design constraint being violated in an implementation of a first-circuit design (e.g., a technology specific netlist with or without a placement solution).
136
Patent
Placement of clock objects under constraints
Srinivasan Dasasathyan,Guenter Stenz,Sudip K. Nag +2 more
- 08 Aug 2002
TL;DR: In this article, the application of network flow techniques to constrained optimization problems is disclosed, and specific applications of the invention to the placement of tristate buffers and clocks in integrated circuits are disclosed.
129
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