Patent
Method for adding contact hole etching process window by setting top etching barrier layer
Xubin Jing,Bin Yang,Mingsheng Guo +2 more
- 18 Apr 2012
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TL;DR: In this article, a method for adding a contact hole etching process window by setting a top etching barrier layer is described, where an etching stop layer which is generally positioned at the bottom of a dielectric layer is moved to the top and can be selectively made of silicon nitride.
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Abstract: The invention discloses a method for adding a contact hole etching process window by setting a top etching barrier layer. According to the method, an etching stop layer which is generally positioned at the bottom of a dielectric layer is moved to the top and can be selectively made of silicon nitride. The method adopts the following basic flows of: firstly, normally etching to reach the height of a silicon gate; secondly, additionally arranging a mask plate of which the area contains holes on a substrate; selectively etching the contact hole by using a top film as a hard barrier layer, wherein the general etching depth is about 800A, the etching stop layer can be stripped in the subsequent CMP (Chemical Mechanical Polishing) engineering or can be certainly retained and the etching stop layer has no influence on the subsequent engineering. Although one extra photoetching work procedure is additionally arranged, a process window of the flow can be greatly increased and the area of a chip is reduced.
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Citations
Patent
Via hole manufacturing method, array substrate and manufacturing method thereof and display device
Yuan Zhidong
- 20 Jul 2016
TL;DR: In this paper, a via hole manufacturing method, an array substrate and a manufacturing method thereof and a display device are presented, which enables the etching time of forming all the via holes and an electrostatic discharge (ESD) generation probability to be reduced, and the production efficiency and yield to be improved.
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Patent
Method of forming via hole, array substrate and method of forming the same and display device
Yuan Zhidong
- 16 Aug 2018
TL;DR: In this article, a method of forming a via hole, an array substrate and a display device is presented, which includes a pattern of a first via hole and an upper-part etched structure of a second via hole simultaneously on a base substrate through a first patterning process by using a first mask.
Patent
Via hole forming method, array substrate and forming method therefor, and display device
Yuan Zhidong
- 02 Nov 2017
TL;DR: In this article, a via hole forming method is proposed to construct a pattern of a first via hole and an upper etching structure of a second via hole by means of a patterning process.
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Contact hole forming process
Peng Xintang,Wang Yongjin,Yang Dengjun +2 more
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TL;DR: The contact hole forming process includes following steps of: providing a semiconductor substrate; setting four, the first, the second, the third and the fourth, grid conductor structures with the second one and the third one being positioned in an active region; forming one metal wire layer on the substrate surface between the second and third grid conductor structure, forming one inner dielectric material layer with flat surface on the whole surface of the substrate to cover the metal wires layer and fill the gap between the first and the second grid conductors; and finally forming three contact holes inside the inner Dielect
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Patent
Surface channel PMOS device with self-aligned contact hole and manufacturing method
Wensheng Qian
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TL;DR: In this paper, a surface channel PMOS device with a self-aligned contact hole was presented, where a silicon oxide gate covering layer was adopted to replace the single silicon nitride gate cover layer.
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