Patent
Method and system for supporting peripheral component interconnect (PCI) peer-to-peer access across a PCI host bridge supporting multiple PCI buses
Richard Allen Kelley,Danny Marvin Neal,Steven Mark Thurber +2 more
- 30 Jun 1998
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TL;DR: In this article, a method and system for supporting multiple Peripheral Component Interconnect (PCI) local buses through a single PCI host bridge having multiple PCI interfaces within a data-processing system are disclosed.
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Abstract: A method and system for supporting multiple Peripheral Component Interconnect (PCI) local buses through a single PCI host bridge having multiple PCI interfaces within a data-processing system are disclosed. In accordance with the method and system of the present invention, a processor and a system memory are connected to a system bus. First and second PCI local buses are connected to the system bus through a PCI host bridge. The first and second PCI local buses have sets of in-line electronic switches, dividing the PCI local buses into PCI local bus segments supporting a plurality of PCI peripheral component slots for connecting PCI devices. The sets of in-line electronic switches are open and closed in accordance with bus control logic within the PCI host bridge allowing up to fourteen or more PCI peripheral component slots for connecting up to fourteen PCI devices to have access through a single PCI host bridge to the system bus. An internal PCI-to-PCI bridge is provided to allow a PCI device to share data with another PCI device as peer-to-peer devices across the first and second PCI local bus segments.
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Citations
Patent
Data transmission circuit for memory subsystem, has switching circuit that selectively connects or disconnects two data bus segments to respectively enable data transmission or I/O circuit connection
Roy Greeff,David K. Ovard,Terry R. Lee +2 more
- 29 Jun 2001
TL;DR: In this article, a method and associated apparatus is provided for improving the performance of a high speed memory bus using switches, where switches disconnect unused bus segments during operations so that communicating devices are connected in an substantially point-to-point communication path.
84
Patent
Peripheral bus switch having virtual peripheral bus and configurable host bridge
Laurent R. Moll
- 14 Oct 2003
TL;DR: A peripheral bus switch includes a virtual peripheral bus, a plurality of bridges, and a configurable host bridge as mentioned in this paper, which couples on a first side to the virtual bus and supports connection on a second side to a peripheral bus fabric.
62
Patent
System and method of mastering a serial bus
Weiyun Sun,Richardo Espinoza-Ibarra +1 more
- 24 Sep 2002
TL;DR: In this paper, a serial bus is monitored in order to detect a quiescent period on the bus, and the bus signals to a first master device of the serial bus are interrupted to isolate the first bus master from the rest of the bus.
54
Patent
Method and apparatus using switches for point to point bus operation
Roy Greeff,David K. Ovard,Terry R. Lee +2 more
- 29 Jun 2001
TL;DR: In this article, a method and associated apparatus is provided for improving the performance of a high speed memory bus using switches, where switches disconnect unused bus segments during operations so that communicating devices are connected in an substantially point-to-point communication path.
51
Patent
Efficient bus utilization in a multiprocessor system by dynamically mapping memory addresses
Sheng Hung Wang,Simon S. Kim +1 more
- 12 Nov 2003
TL;DR: In this paper, a slave interface circuit includes a slave access circuit and a slave bus decoder, which enables the one of the P slave devices to connect to one of K slave buses.
46
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