Patent
Method and apparatus for transition direction coding
Steven F. Nugent
- 30 Dec 1992
9
TL;DR: In this paper, a method and apparatus for encoding data in the context of a digital system for communicating binary information, including code words, over a communications channel is presented, where a change in the bit pattern between a bit and a prior adjacent bit represents a transition having a direction.
read more
Abstract: The present invention provides a method and apparatus for encoding data in the context of a digital system for communicating binary information, including code words, over a communications channel. The information communicated over the channel is synchronized by a system clock producing a plurality of system clock pulses having edges associated with the binary information, where a change in the bit pattern between a bit and a prior adjacent bit represents a transition having a direction. The present invention encodes data words of n-bits each into a plurality of code words of m-bits each by selecting from the set of m-bit binary numbers those binary numbers in which each bit either experiences a transition in the same direction as the system clock edge associated with that bit or experiences no transition from a prior adjacent bit to that bit. Each of the selected binary numbers is a code word. Each data word is preferably associated with a code word. Data words are preferably formed into a message, and each code word associated with each data word of the message is longitudinally serialized so that each code word is represented by a serial bit pattern. The associated code words of the message are then transmitted in parallel with each other in a plurality of groups or "stacks".
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Citations
Patent
Frequency responsive bus coding
John Wilson,Aliazam Abbasfar,John Eble,Lei Luo,Jade M. Kizer,Carl W. Werner,Wayne Dettloff +6 more
- 18 Jun 2009
TL;DR: In this article, the authors propose a data bus inversion (DBI) circuit that selectively inverts all lines of the data bus to avoid undesirable frequency conditions such as a resonant condition that may lead to degradation in system performance.
84
Patent
Fast AtA-compatible drive interface with error detection and/or error correction
John Chester Masiewicz,Sean R. Atsatt,Jeffrey Alan Miller +2 more
- 10 Mar 1998
TL;DR: In this paper, an ATA-compatible drive interface with error correction and detection capabilities is disclosed. But the interface does not support data integrity checking and does not require additional words in a data transfer, and data correction feature does not need new data transfer protocols or additional data transfer overhead.
73
Patent
Transmission and reception interface and method of data transmission
Kiehl Oliver
- 16 Jul 2002
TL;DR: In this paper, an N-bit word is produced from an M-bit code received on an Mbit line by comparing the levels at the two bit positions of the code word to obtain a first value, and then decoding the M-bits code word responsive to detecting that the first value is opposite to the second value.
46
Patent
Combining a clock signal and a data signal
Gyudong Kim,Ook Kim,Min-Kyu Kim,Bruce Kim,Seung Ho Hwang +4 more
- 15 Mar 2002
TL;DR: In this paper, a method of transmitting data in a system including at least one data channel and a separate clock channel is disclosed, which involves combining a clock signal to be transmitted on the clock channel with a data signal to generate a combined clock and data signal.
35
Patent
Apparatus and method for efficient data transport using transparent framing procedure
Steven Scott Gorshe
- 05 Jul 2002
TL;DR: In this paper, the authors present a method and/or system for mapping a protocol including data and a limited number of control codes to an efficient encoding protocol for carrying on various other networks, particularly those with parallel processing.
26
References
Patent
Synchronous optical transmission system
Raymond Eugene Tyrrell,Bishop Lamar O,William Edward Powell,Dale Lee Krisher,William H. Stephenson,Briscoe Rodney M,Hal Andrew Thorne,Claude M. Hurlocker,Paul V Runyon,Timothy James Williams,Joseph E. Sutherland,William B Fox,Michael J. Gingell,Kenneth J. Stoia,William J. Fox,Jeffrey P. Jones,Richard M. Czerwiec,Ertugrul Baydar,Heinrich T. Sonnenberg,Richard William Peters,Gus Clint Sanders,Jr Richard J Sanders,Francis G. Noser,Joseph L. Smith,Jak Yaemsiri,Camille A. Abu-Saba,Patrick M. Farrell,Wenkwei Rou,Victor W. Wilkerson,Mohammad S. Arani,Stephen C. Dunning,Keith L Bernhardt,Dana Merrill,Michael Sutton +33 more
- 11 May 1990
TL;DR: In this article, a synchronous optical transmission system for interfacing SONET formatted channels to lower speed channels in either a single-input single-out (SISO) or multiple-output (MISO) format is presented.
293
Patent
CMOS clock-phase synthesizer
Mel Bazes
- 01 Mar 1990
TL;DR: In this article, an integrated circuit apparatus for changing the phase relationship between at least one clock-phase output and a reference clock is disclosed, coupled with a waveform synthesizer.
44
Patent
Increased resolution logic analyzer using asynchronous sampling
B. J. Moore,William E. Shoemaker +1 more
- 12 May 1986
TL;DR: In this paper, a logic analyzer instrument that allows the acquisition of digital samples from a plurality of logic signals in a large mainframe computer, or other system under test, in a manner that the signals can be reconstructed for viewing and analysis of the relationship between them is presented.
31
Patent
Apparatus and technique for testing IC memories
Robert D. Catiller
- 26 May 1981
TL;DR: In this paper, a technique for testing the access time of electronic storage arrays such as bistable storage cells fabricated in accordance with integrated circuit technology is described, where a test pattern generator generates addresses on an "increment-complement" system and applies these addresses to a memory such as a PROM being tested.
20
Patent
Serial pulse-code-modulated retiming system
Abraham M Gindi,Ju-Hi J. Hong,William Karl Stelzenmuller +2 more
- 15 May 1975
TL;DR: In this paper, an improved clock retiming system for pulse coded data is provided in which the clock signals are extracted from the encoded data and first and second signals of the same amplitude and frequency but of different phase are generated from the clock signal.
12
Related Papers (5)
Hiroshi Ogawa,Tamotsu Yamagami +1 more
- 10 Sep 1982
Masaaki Kato
- 06 Mar 1984
Daal Andreas Johannes Wilhelmu
- 29 Jul 1980