Memory Reduction Methodology for Distributed-Arithmetic-Based DWT/IDWT Exploiting Data Symmetry
TL;DR: By exploiting the inherent symmetry of the discrete wavelet transform (DWT) algorithm and consequently storing only the nonrepetitive combinations of filter coefficients, the size of required memory can be significantly reduced.
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Abstract: In this brief, we show that by exploiting the inherent symmetry of the discrete wavelet transform (DWT) algorithm and consequently storing only the nonrepetitive combinations of filter coefficients, the size of required memory can be significantly reduced. Subsequently, a memory-efficient architecture for DWT/inverse DWT is proposed. It occupies 6.5-mm2 silicon area and consumes 46.8-muW power at 1 MHz for 1.2 V using 0.13-mum standard cell technology.
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Citations
•Journal Article
VLSI Implementation of Discrete Wavelet Transform
TL;DR: A VLSI architecture of the recursive pyramid algorithm (RPA) for the DWT is proposed using a group of input delay units and a control unit and the architecture is implemented using only one set of parallel filters.
60
VLSI Architectures for Discrete Wavelet Transforms
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- 28 Jan 2005
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Coordinate Rotation Based Low Complexity N-D FastICA Algorithm and Architecture
TL;DR: The proposed algorithm can merge the two key steps of conventional FastICA-preprocessing and update and is therefore capable of reducing the hardware complexity of theventional FastICA significantly as demonstrated in this paper.
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A Pipeline VLSI Architecture for High-Speed Computation of the 1-D Discrete Wavelet Transform
TL;DR: The proposed scheme for the design of a high-speed pipeline VLSI architecture for the computation of the 1-D discrete wavelet transform (DWT) with little or no overhead on the hardware resources by maximizing the inter- and intrastage parallelisms of the pipeline is proposed.
Area- and Power-Efficient Design of Daubechies Wavelet Transforms Using Folded AIQ Mapping
Ashraful Islam,Khan A. Wahid +1 more
TL;DR: An efficient design of a shared architecture to compute two 8-point Daubechies wavelet transforms based on a two-level folded mapping technique developed on the factorization and decomposition of transform matrices exploiting the symmetrical structure is presented.
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TL;DR: The central concept of sparsity is explained and applied to signal compression, noise reduction, and inverse problems, while coverage is given to sparse representations in redundant dictionaries, super-resolution and compressive sensing applications.
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Keshab K. Parhi,T. Nishitani +1 more
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A Scalable Wavelet Transform VLSI Architecture for Real-Time Signal Processing in High-Density Intra-Cortical Implants
TL;DR: Results indicate that signal integrity is not compromised by quantization down to 5-bit filter coefficient and 10-bit data precision at intermediate stages, and results from analog simulation and modeling show that a hardware-minimized computational core executing filter steps sequentially is advantageous over the pipeline approach commonly used in DWT implementations.
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Jer Min Jou,Yeu-Horng Shiau,Chin-Chi Liu +2 more
- 06 May 2001
TL;DR: In this article, two efficient VLSI architectures for the biorthogonal wavelet transform are proposed, one constructed by the filter bank implementation and another by the lifting scheme.
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