Proceedings Article10.1109/ISCAS.2010.5537637
Memory-reduced MAP decoding for double-binary convolutional Turbo code
Jinjin He,Zhongfeng Wang,Huaping Liu +2 more
- 03 Aug 2010
- pp 469-472
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TL;DR: A memory-reduced VLSI architecture for the decoding of double-binary convolutional Turbo code (DB CTC) using maximum a posteriori probability (MAP) algorithm based on the new formulation of BMs, which leads to 50% reduction of the memory size for BMs.
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Abstract: This paper presents a memory-reduced VLSI architecture for the decoding of double-binary convolutional Turbo code (DB CTC) using maximum a posteriori probability (MAP) algorithm. For such kind of soft-in soft-out (SISO) decoding, the branch metrics (BMs) γ become the dominant factor in determining the overall required memory size inside the SISO decoder. We propose to decompose each BM into a information metric and a parity metric, which leads to 50% reduction of the memory size for BMs. We further modify the MAP algorithm based on the new formulation of BMs. The new MAP algorithm reveals that: 1) the partitioning of BMs does not introduce any computational overhead when the MAP algorithm is modified; 2) the extrinsic metrics are independent from a posteriori log-likelihood ration, which is attractive for low-power SISO decoder design.
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Citations
A memory reduced decoding scheme for double binary convolutional turbo code based on forward recalculation
Ming Zhan,Liang Zhou +1 more
- 08 Oct 2012
TL;DR: An iterative decoding scheme with small memory size is proposed, based on an improved maximum a posterior probability (MAP) algorithm, and stores part of the backward metrics in the state metrics cache (SMC).
4
Memory reduced MAP decoding for double-binary turbo decoder
TL;DR: The proposed branch metric recovery scheme to reduce the memory requirement of MAP decoding for double-binary convolutional turbo code and shows the extremely low overhead compared to the huge memory reduction.
2
A low-memory intensive decoding architecture for double-binary convolutional turbo code
Ming Zhan,Liang Zhou,Jun Wu +2 more
TL;DR: Owing to a compare-select--recalculate processing (CSRP) module in the proposed decoding architecture, the unstored state metrics are recalculated by simple operations, while maintaining near optimal decoding performance.
2
Design and Implementation of Convolution Encoder
Rakhi B. Menon,Gnana Sheela K +1 more
- 01 Jan 2015
TL;DR: Convolution encoding with forward error correction Viterbi decoding is designed and implementation parameters for the decoder have been determined through simulation and theDecoder should be implemented on a Xilinx FPGA SPARTAN 3E Kit.
References
•Journal Article
Optimal decoding of linear codes for minimizing symbol error rate
TL;DR: The general problem of estimating the a posteriori probabilities of the states and transitions of Markov source observed through a discrete memoryless channel is considered.
6.8K
Optimal decoding of linear codes for minimizing symbol error rate (Corresp.)
TL;DR: The general problem of estimating the a posteriori probabilities of the states and transitions of a Markov source observed through a discrete memoryless channel is considered and an optimal decoding algorithm is derived.
5.1K
Comparative study of turbo decoding techniques: an overview
Jason Woodard,Lajos Hanzo +1 more
TL;DR: An overview of the novel class of channel codes referred to as turbo codes, which have been shown to be capable of performing close to the Shannon limit, is provided.
Improving the max-log-MAP turbo decoder
TL;DR: Simulations using the 1MT-2000/3GPP parameters demonstrate that this method gives /spl sim/0.2 to 0.4 dB performance gain compared to the standard max-log-MAP algorithm.
314
Non-binary convolutional codes for turbo coding
Claude Berrou,Michel Jezequel +1 more
TL;DR: It is shown that quaternary codes can be advantageous, both from performance and complexity standpoints, but that higher-order codes may not bring further improvement.
139