Memory interference models for a multi-microprocessor system with a shared bus and a single external common memory

TL;DR: Markovian models are developed for the performance analysis and comparison of several single bus multiprocessor architectures, introducing simplifying assumptions that allow a compact Markovian system description.

TL;DR: A model for predicting multiprocessor performance on iterative algorithms is developed and illustrates the significant impact on performance of decomposing an algorithm into parallel processes.

TL;DR: A new class of queuing models, called Synchronized Queuing Networks, is proposed for evaluating the performance of multiprogrammed and multitasked multiprocessor systems, where workloads consists of parallel programs of similar structure and where the scheduling discipline is first-come-first-serve.

TL;DR: An allocation model for mapping a real-time application to certain k-processor multiprocessor systems is developed and analyzed and experience suggests that it can be used effectively for the performance evaluation of application-distributed system pairs.

TL;DR: This interface is suitable for dealing with the line-like-behavior that the system needs to manage, but it ought to require that dequeue return the highest priority item in the queue, regardless of how long it has been in the structure.

TL;DR: This book is an introduction to the probabilistic treatment of mass servicing.

TL;DR: A simple automatic design program is proposed which optimally configures computer structures from a set of available components and relates the instruction execution rate to the memory and processor speeds, their number, and their interconnection.