Patent
Memory fault correction system and method
Joseph M. Jeddeloh
- 16 Dec 1996
31
TL;DR: In this article, a memory fault correction system enables plural data bit errors in a single data word to be corrected in an efficient manner by dividing each data word into a plurality of sub-words and creating a separate error correction code for each of the subwords.
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Abstract: A memory fault correction system enables plural data bit errors in a single data word to be corrected in an efficient manner. The system divides each data word into a plurality of sub-words and creates a separate error correction code for each of the sub-words. Each of the error correction codes includes a plurality of check bits with check bit values based on the data bit values of the corresponding sub-word of the data word. The computer system includes a plurality of error correction modules each performing error correction on a separate sub-word of the data word. A memory controller rearranges the data bits of the data word when forming the sub-words such that consecutive data bits are arranged in separate sub-words.
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Citations
Patent
Memory controller for multilevel cell memory
Fujitsu Limited Keisuke Kawasaki-shi Kanagawa Kanazawa,Hiroaki Watanabe,Fujitsu Limited Yoshinobu Kawasaki-shi Kanagawa Higuchi,Fujitsu Limited Hideki Kawasaki-shi Kanagawa Arakawa,Okumura Yoshiki,Sekino Yutaka +5 more
- 18 Mar 2002
TL;DR: In this paper, a N-level cell memory controlled by the memory controller of the invention has an internal configuration in which the plurality of data input/output terminals connected to the second data bus are separated into first through Mth data input and output terminal groups, such that there is no redundancy in the n bits of data associated with one Nlevel cell.
141
Patent
Variable strength ECC
William H. Radke
- 31 Aug 2006
TL;DR: In this paper, the authors describe data detection and correction in memory controllers, memory systems, and/or non-volatile memory devices by allowing the number of ECC check bytes being utilized to be varied to increase or decrease the ECC coverage.
128
Patent
Error detection/correction code which detects and corrects component failure and which provides single bit error correction subsequent to component failure
Robert E. Cypher
- 28 Jun 2002
TL;DR: In this paper, a memory controller comprises a check bit encoder circuit and a check/correct circuit, which are coupled to decode the encoded data block and perform at least the detection of (i) and (ii) on the data block.
120
Patent
Erase block data splitting
David Eggleston,Anthony Moschopoulos,Michael Murray,Brady L. Keays +3 more
- 24 Jun 2003
TL;DR: In this article, a distributed erase block sector sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks is presented, which enhances fault tolerance and reliability of the Flash memory device.
114
Patent
Non-systematic coded error correction
William H. Radke,Shuba Swaminathan,Brady L. Keays +2 more
- 28 Apr 2005
TL;DR: In this paper, improved memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory systems or devices by encoding the data bits of a memory row or block in a non-systematic ECC code.
107
References
Patent
Error correction system for n bits using error correcting code designed for fewer than n bits
David G. Abdoo,J. David Cabello +1 more
- 02 Oct 1992
TL;DR: In this article, two identical error detection and correction (EDC) circuits are connected to the system memory array, and each EDC circuit is connected to half of the data bits in alternating pairs.
72
Patent
Method and apparatus for effecting multiple error correction in a computer memory
Michael K. Benton,John L. Janssen,Andrew T. Jennings +2 more
- 08 Jun 1990
TL;DR: In this paper, a memory system provides a method for error detection and correction, where large data words are divided into multiple error correction zones, and one zone from each of two or more words are combined to form an error domain.
63
Patent
Multiple-bit error correction in computer main memory
Donald Smelser
- 08 Dec 1995
TL;DR: In this paper, an EDC with 128-bits of data and a check bit field 41-bits wide, using a BCH code, constructed in ASIC sea-of-gates technology using about 87,000 logic gates, can correct 5-bits in error and can detect 6-bits.
60
Patent
Data error detection and correction system
William J. Walker,Alan L. Goodrum,Dale J. Mayer +2 more
- 14 Oct 1994
TL;DR: In this article, a system that performs error correction and detection of data read from memory in a computer system having a processor bus and a system bus is presented, where a pair of data buffers are used to interface between the memory and the processor data bus or the system data bus.
42
Patent
Method and apparatus for correction errors in a memory
Gerard Barucchi,Philippe Cuny,Philippe Klein,Olivier Maurel,Jean-Luc Peter +4 more
- 18 Nov 1993
TL;DR: The method and apparatus for correcting one B-bit block in error in a memory organized in words comprising N Bbit blocks consist of appending to the data bits to be written into the memory words a limited number of error correction bits computed from a depopulated parity check matrix.
19