Memory evolution: Multi-functioning Unified-Random Access Memory (URAM)
Yang-Kyu Choi,Jin-Woo Han +1 more
- 30 Dec 2008
- pp 831-834
TL;DR: A new paradigm for silicon memory technology is proposed, as multi-functional operation is processed in a single memory cell, as unified-random access memory (URAM), as the paradigm shift from `scaling¿ to `multi-function¿ will create new value and continue the evolution of silicon memorytechnology.
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Abstract: A new paradigm for silicon memory technology is proposed. A technological breakthrough that will overcome the saturation in revenue obtained from `scaling?, a novel type of fusion memory is presented. A high-speed DRAM and non-volatile flash memory are integrated in a single memory transistor. The memory cell is named unified-random access memory (URAM), as multi-functional operation is processed in a single memory cell. The paradigm shift from `scaling? to `multi-function? will create new value and continue the evolution of silicon memory technology.
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Figures
Figure 4. Measured programming and erasing characteristics of Id-Vg. P/E is carried out by a Fowler-Nordheim mechanism. 
Figure 5. Cross-sectional schematics and energy band lineup for various substrates. (a) SOI substrate, (b) buried n-well, and (c) buried Si1-yCy. 
Figure 3. TEM images of URAM. (a) Bird eye’s veiw of URAM and gate dielectric O/N/O. (b) URAM on SOI substrate. (c) URAM on buried n-well substrate. (d) URAM on buried Si1-yCy substrate. 
Figure 2. Schematic view of URAM concept. SONOS memory and 1T-DRAM operation are implemented in a memory cell. 
Figure 6. Measured programming and erasing characteristics of 1T-DRAM. For programming, impact ionization voltages of VD=1.5Vand VG=1V for SOI, and VD=2Vand VG=1V for bulk are used. For erasing, forward junction voltage of VD=-1V for all devices is used. During all operations, the substrate voltages are VSub=0V for SOI, and VSub=0.3V for n-well and Si1-yCy. 
Figure 7. ID-VD curves after 1T-DRAM operation. The programming disturbance between impact ionization for 1T-DRAM and charge trapping for non-volatile memory is found to be negligible.
