Proceedings Article10.1109/ICASSP.2007.366159
Memory Efficient LDPC Code Design for High Throughput Software Defined Radio (SDR) systems
Yuming Zhu,Chaitali Chakrabarti +1 more
- 15 Apr 2007
- Vol. 2, pp 9-12
TL;DR: A procedure for architecture-aware LDPC code design which minimize the number of global memory accesses in a memory constrained system is derived and results in reduction in the numberof iterations and thereby increases the throughput significantly.
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Abstract: Low-density parity-check (LDPC) codes have been adopted in the physical layer protocol of many communication systems because of their superior performance. A direct implementation of the LDPC decoder on an existing platform, such as a software defined radio (SDR), is likely to be inefficient. Our approach is to design the LDPC code in a way that takes into account the constraints imposed by the existing architecture, without compromising the communication performance. In this paper, a procedure for architecture-aware LDPC code design which minimize the number of global memory accesses in a memory constrained system is derived. The procedure is built on top of existing super-code based LDPC code design. The proposed code construction procedure also results in reduction in the number of iterations and thereby increases the throughput significantly.
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Citations
Satellite Communications in the New Space Era: A Survey and Future Challenges
Oltjon Kodheli,Eva Lagunas,Nicola Maturo,Shree Krishna Sharma,Bhavani Shankar,Jesus Fabian Mendoza Montoya,Juan Carlos Merlano Duncan,Danilo Spano,Symeon Chatzinotas,Steven Kisseleff,Jorge Querol,Lei Lei,Thang X. Vu,George Goussetis +13 more
TL;DR: In this article, the authors present a survey of the state of the art in satellite communications, while highlighting the most promising open research topics, such as new constellation types, on-board processing capabilities, non-terrestrial networks and space-based data collection/processing.
Architecture-Aware LDPC Code Design for Multiprocessor Software Defined Radio Systems
Yuming Zhu,Chaitali Chakrabarti +1 more
TL;DR: This paper presents a general procedure for designing low density parity check (LDPC) codes for multiprocessor software defined radio platforms and shows how code construction can be used to significantly reduce the number of routing conflicts.
12
•Posted Content
Satellite Communications in the New Space Era: A Survey and Future Challenges
Oltjon Kodheli,Eva Lagunas,Nicola Maturo,Shree Krishna Sharma,Bhavani Shankar,J. F. Mendoza Montoya,J. C. Merlano Duncan,Danilo Spano,Symeon Chatzinotas,Steven Kisseleff,Jorge Querol,Lei Lei,Thang X. Vu,George Goussetis +13 more
TL;DR: The present survey aims at capturing the state of the art in SatComs, while highlighting the most promising open research topics, and a number of future challenges and the respective openResearch topics are described.
10
References
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Low-Density Parity-Check Codes
Robert G. Gallager
- 01 Jan 1963
TL;DR: A simple but nonoptimum decoding scheme operating directly from the channel a posteriori probabilities is described and the probability of error using this decoder on a binary symmetric channel is shown to decrease at least exponentially with a root of the block length.
On the design of low-density parity-check codes within 0.0045 dB of the Shannon limit
TL;DR: Improved algorithms are developed to construct good low-density parity-check codes that approach the Shannon limit very closely, especially for rate 1/2.
A reduced complexity decoder architecture via layered decoding of LDPC codes
D.E. Hocevar
- 06 Dec 2004
TL;DR: The previously devised irregular partitioned permutation LDPC codes have a construction that easily accommodates a layered decoding and it is shown that the decoding performance is improved by a factor of two in the number of iterations required.
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A FPGA and ASIC implementation of rate 1/2, 8088-b irregular low density parity check decoder
Yanni Chen,D.E. Hocevar +1 more
- 01 Dec 2003
TL;DR: This paper presents an implementation of irregular low density parity check decoder using both FPGA and ASIC and the partly parallel structure, memory management, message alignment and addressing generation schemes needed to realize the underlying graph connectivity will be discussed.
99
Memory-efficient sum-product decoding of LDPC codes
H. Sankar,Krishna R. Narayanan +1 more
TL;DR: The proposed decoding algorithm can be analyzed using density evolution; further, it is shown how to design good LDPC codes using this, and results show that this algorithm provides almost the same performance as the conventional sum-product decoding ofLDPC codes.
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