Memory controller interface

TL;DR: In this article, a wireless phone memory controller is described that, comprises a first interface circuit (106) configured to be coupled to wireless phone nonvolatile memory (104), a second interface circuit coupled to volatile memory (105), a first processor interface configured to provide the first p-ocessor with access to the wireless phone volatile memory, a second processor interface configurable to copy at least a portion of wireless phone NVRAM data to the WPCN, and a controller circuit (103) configurable for copying at least some of WPRAM data.

TL;DR: In this paper, the authors define at least one of the plurality of memory portions other than the certain portions as a retired memory portion for at least a first duration of time, and they define a controller operative to reserve for data retention purposes.

TL;DR: In this article, a system for storing a plurality of logical pages in a set of at least one flash device, each flash device including an erase block in the set of erase blocks, is described.

TL;DR: In this paper, a method for programming a plurality of data sequences into a corresponding plurality of flash memory functional units using a programming process having at least one selectable programming duration-controlling parameter controlling the duration of the programming process for a given data sequence is presented.

TL;DR: In this article, a method and apparatus for handling the refresh of a DRAM array or other memory array requiring periodic refresh operations so that the refresh does not require explicit control signaling nor handshake communication between the memory array and the memory controller is presented.

TL;DR: In this paper, a system and method for booting a computing device using a NAND flash memory is described, where the boot code stored in the NAND Flash memory is transferred to a RAM for execution by the CPU.

TL;DR: In this paper, a method and apparatus for protecting a computer system is described, where a boot block is used to validate the BIOS, CMOS and NVRAM of a system.

TL;DR: In this paper, the authors present a data processing system that includes a system bus, a bus master coupled to the system bus and a memory controller bus operating independent of the bus to transfer data between the first memory controller and the second memory controller.