Patent
Memory controller for multilevel cell memory
Fujitsu Limited Keisuke Kawasaki-shi Kanagawa Kanazawa,Hiroaki Watanabe,Fujitsu Limited Yoshinobu Kawasaki-shi Kanagawa Higuchi,Fujitsu Limited Hideki Kawasaki-shi Kanagawa Arakawa,Okumura Yoshiki,Sekino Yutaka +5 more
- 18 Mar 2002
141
TL;DR: In this paper, a N-level cell memory controlled by the memory controller of the invention has an internal configuration in which the plurality of data input/output terminals connected to the second data bus are separated into first through Mth data input and output terminal groups, such that there is no redundancy in the n bits of data associated with one Nlevel cell.
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Abstract: A N-level cell memory controlled by the memory controller of the invention have an internal configuration in which the plurality of data input/output terminals connected to the second data bus are separated into first through Mth data input/output terminal groups, such that there is no redundancy in the n bits of data associated with one N-level cell. Together with this, the memory controller separates the plurality of data bits on the first data bus into first through Mth data groups, the ECC circuits generate error-correction codes for each of these data groups, and the first through Mth data groups and first through Mth error correction codes are input to the first through Mth data input/output terminals of the N-level cell memory, via the second data bus.
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Citations
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135
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Patent
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Patent
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31