Memory controller for handling data transfers which exceed the page width of DDR SDRAM devices

TL;DR: In this paper, a memory controller includes a pair of input command decoders and two multiplexers, and the data transfer request relates to a read or write burst which will burst over a page of the memory.

Abstract: A memory controller includes a pair of input command decoders and a pair of multiplexers. If the memory controller receives a data transfer request related to a read or write burst which will stay within a page of memory, the first input command decoder circuit generates a first input command which is then passed, in sequence, by the first and second multiplexers. Conversely, if the data transfer request relates to a read or write burst which will burst over a page of the memory, the second input command decoder circuit generates second and third input commands. The second input command passes through the second multiplexer circuit while the third input command is held in a command register. The third input command is subsequently passed through the first and second multiplexers.