Patent
Memory caching in data processing
Ezra Rabin,Solomon Ezra +1 more
- 08 May 2006
6
TL;DR: In this paper, a data processor comprises a main memory, an instruction cache and a data cache; instruction fetch logic operable to search the instruction cache for a required instruction; and if the required instruction is not present in the data cache, to retrieve it from the main memory.
read more
Abstract: A data processor comprises a main memory; an instruction cache and a data cache; instruction fetch logic operable to search the instruction cache for a required instruction; and if the required instruction is not present in the instruction cache, to search the data cache; and if the required instruction is not present in the data cache, to fetch the required instruction from the main memory to the instruction cache; data write logic operable to write a data value into the data cache at a data address and, if that address is also represented in the instruction cache, to write that data value into the instruction cache; and cache control logic operable to transfer data from the data cache to the main memory.
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Citations
Patent
Systems, methods, and interfaces for adaptive persistence
Vikram Joshi,Yang Luan,Michael F. Brown,David Flynn,Brent Lim Tze Hao,Jerene Zhe Yang,Prashanth Radhakrishnan +6 more
- 29 Aug 2013
TL;DR: A storage module may be configured to service I/O requests according to different persistence levels as mentioned in this paper, which relate to the storage resource(s) used to service the request, the configuration of the storage resources, the storage mode of the resources, and so on.
60
Patent
Systems and methods for storage virtualization
Jerene Zhe Yang,Brent Lim Tze Hao,Vikram Joshi,Michael F. Brown,Prashanth Radhakrishnan,David Flynn,Bhavesh Mehta +6 more
- 04 Apr 2014
TL;DR: In this paper, an I/O manager may be configured to service requests pertaining to ephemeral data of a virtual machine using a storage device that is separate from and/or independent of a primary storage resource to which the request is directed.
20
Patent
Systems, methods, and interfaces for adaptive cache persistence
Vikram Joshi,David Flynn,Yang Luan,Michael F. Brown +3 more
- 14 Mar 2013
TL;DR: A storage module may be configured to service I/O requests according to different persistence levels as mentioned in this paper, which relate to the storage resource(s) used to service the request, the configuration of the storage resources, the storage mode of the resources, and so on.
16
Patent
Processor, information processing device, information processing method, and system start program
Tatsuhiko Sorai,空井 達彦 +1 more
- 25 Jan 2011
TL;DR: In this paper, the problem of storing an instruction in an instruction cache without fetching the instruction was solved by using the Harvard architecture, where the instruction is temporarily read in a data cache and then transferred to be stored in the instruction cache.
Patent
Method and apparatus for use of a preload instruction to improve efficiency of cache
Sujat Jamil,R. Frank O'Bleness,Russell J. Robideau,Tom Hameenanttila,Joseph Delgross,David E. Miner +5 more
- 26 Jan 2015
TL;DR: In this article, a preloading instruction is inserted after the store instruction but before a dependent load instruction to the address to invalidate a data entry of a cache array at an address of the cache array corresponding to the target address.
References
Patent
Dual cache for independent prefetch and execution units
Richard F. Thompson,Daniel J. Disney,Swee-meng Quek,Eric C. Westerfeld +3 more
- 16 Oct 1986
TL;DR: In this article, a pipelined digital computer processor system is provided comprising an instruction prefetch unit (IPU,2) for prefetching instructions and an arithmetic logic processing unit (ALPU, 4) for executing instructions.
76
Patent
System for flushing instruction-cache only when instruction-cache address and data-cache address are matched and the execution of a return-from-exception-or-interrupt command
Raj K. Ramanujan,Peter J. Bannon,Simon C. Steely +2 more
- 21 Jun 1990
TL;DR: In this paper, a method and apparatus for optimizing the performance of a multiple cache system computer having separate caches for data and instructions in which all writes to the data cache are monitored is presented.
22
Patent
Explicit store-to-instruction-space instruction for self-modifying code and ensuring memory coherence between instruction cache and shared memory using a no-snoop protocol
Marc Tremblay
- 05 May 2000
TL;DR: In this article, a store-to-instruction-space instruction is presented, where a unique opcode indicates that a data value is to be written to an instruction space in main memory.
15
Patent
Cache memory device constituting a memory device used in a computer
Tsukasa Matoba,Takeshi Aikawa,Kenichi Maeda,Mitsuo Saito,Okamura Mitsuyoshi +4 more
- 25 Mar 1988
TL;DR: In this article, a cache memory device comprises a data cache memory, an instruction cache memory and an instruction code area change processor, which decides whether writing access to the cache memory by a processor is to a data area or to an instruction area of a main memory.
11
Patent
Cache memory device
Takeshi Aikawa,Kenichi Maeda,Tsukasa Matoba,Okamura Mitsuyoshi,Mitsuo Saito +4 more
- 25 Mar 1988
TL;DR: In this article, an instruction code area change detector decides whether writing access to the data cache memory by a processor is to a data area or to an instruction area of a main memory.
9