Journal Article10.1109/TVLSI.2014.2332465
Low-Power Programmable PRPG With Test Compression Capabilities
Michal Filipek,Grzegorz Mrugalski,Nilanjan Mukherjee,Benoit Nadeau-Dostie,Janusz Rajski,Jedrzej Solecki,Jerzy Tyszer +6 more
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TL;DR: An LP test compression method that allows shaping the test power envelope in a fully predictable, accurate, and flexible fashion by adapting the PRESTO-based logic BIST (LBIST) infrastructure is proposed.
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Abstract: This paper describes a low-power (LP) programmable generator capable of producing pseudorandom test patterns with desired toggling levels and enhanced fault coverage gradient compared with the best-to-date built-in self-test (BIST)-based pseudorandom test pattern generators. It is comprised of a linear finite state machine (a linear feedback shift register or a ring generator) driving an appropriate phase shifter, and it comes with a number of features allowing this device to produce binary sequences with preselected toggling (PRESTO) activity. We introduce a method to automatically select several controls of the generator offering easy and precise tuning. The same technique is subsequently employed to deterministically guide the generator toward test sequences with improved fault-coverage-to-pattern-count ratios. Furthermore, this paper proposes an LP test compression method that allows shaping the test power envelope in a fully predictable, accurate, and flexible fashion by adapting the PRESTO-based logic BIST (LBIST) infrastructure. The proposed hybrid scheme efficiently combines test compression with LBIST, where both techniques can work synergistically to deliver high quality tests. Experimental results obtained for industrial designs illustrate the feasibility of the proposed test schemes and are reported herein.
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Citations
Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding
TL;DR: A new low-power (LP) scan-based built-in self-test (BIST) technique is proposed based on weighted pseudorandom test pattern generation and reseeding, which supports both pseud orandom testing and deterministic BIST.
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Power Aware Testing And Test Strategies For Low Power Devices
Franziska Frankfurter
- 01 Jan 2016
TL;DR: Thank you very much for reading power aware testing and test strategies for low power devices.
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Test-cost optimization in a scan-compression architecture using support-vector regression
Zipeng Li,Jonathon E. Colburn,Vinod Pagalone,Kaushik Narayanun,Krishnendu Chakrabarty +4 more
- 09 Apr 2017
TL;DR: An optimization method based on support-vector regression to determine the PRPG length for test-cost reduction in a given scan-compression architecture is proposed and a correlation-based feature selection methodology is proposed to reduce the amount of data needed for the accurate selection of thePRPG length.
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A Low Power Test Pattern Generator for Minimizing Switching Activities and Power Consumption
Jugal Kishore Bhandari,M. Krishna Chaitanya,G. Venkat Rao +2 more
- 01 Jul 2018
TL;DR: This paper presents approach known as low power-positioned complements bits test vector generation (LP-PCBTVG) technique with partially fixed bits sequence and bit insertion techniques which will scale back the massiveness of TPG which can contribute in reducing size of IC.
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Storage-Based Built-In Self-Test for Gate-Exhaustive Faults
TL;DR: This article explores a tradeoff between the amount of stored test data and the comprehensiveness of the test set that can be applied in a specific context that has the following main features: 1) the initial storedtest data is based on a stuck-at test set; 2) the target faults are single-cycle gate-exhaustive faults; and 3).
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