Open Access
Low Power GALS Interface Implementation with Stretchable Clocking Scheme
C Anju,Kirti S Pande +1 more
- 01 Jan 2012
Vol. 9, Iss: 4
TL;DR: A low power GALS interface with stretchable clocking scheme in verilog HDL is implemented and the dynamic power of the interface with and without stretchableClocking with Synopsys Design Compiler is compared.
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Abstract: Complex SoC imply the seamless integration of numerous IPs performing different functions and operating at different clock frequencies The integration of several heterogeneous components into a single system gives rise to new challenges Major issue includes controlling the clock frequencies of the different modules As chips become faster and larger, designers face significant challenges including global clock distribution and power dissipation In-order to achieve global synchronization with high performance and low power conception globally asynchronous locally synchronous (GALS) method is used In GALS, local modules can operate with their own clock and the entire module is communicating asynchronously In this paper we implemented a low power GALS interface with stretchable clocking scheme in verilog HDL and compare the dynamic power of the interface with and without stretchable clocking with Synopsys Design Compiler
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References
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TL;DR: This paper describes a complete design methodology for a globally asynchronous on-chip communication network connecting both locally-synchronous and asynchronous modules and confirmed the validity of the concept by applying it to an ASIC design implementing the Safer crypto-algorithm.
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An asynchronous wrapper with novel handshake circuits for GALS systems
Shengxian Zhuang,Weidong Li,Jonas Carlsson,Kent Palmkvist,Lars Wanhammar +4 more
- 29 Jun 2002
TL;DR: An asynchronous wrapper with novel handshake circuits for data communication to be used in GALS systems and the design methodology is given and the circuits are validated with VHDL and circuits simulation in standard CMOS technology.
24
A low-latency GALS interface implementation
Yuan-Teng Chang,Wei-Che Chen,Hung-Yue Tsai,Wei-Min Cheng,Chang-Jiu Chen,Fu-Chiung Cheng +5 more
- 01 Dec 2010
TL;DR: A small and simple stretchable-clock based GALS wrapper with low-latency in Verilog HDL and synthesized the design with TSMC 0.13µm cell library shows that the wrapper can operate correctly with modules which operate with great different clock frequencies and recommends adding FIFO storage element on the transmission path.
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