Low-power embedded system

TL;DR: In this paper, a low-power embedded system consisting of a first clock unit, a second clock unit and a third clock unit is presented, where the clock switching unit is used for receiving the first clock signal, the second clock signal and the third clock signal.

Abstract: An embodiment of the invention provides a low-power embedded system. The system comprises a first clock unit, a second clock unit, a third clock unit, a clock switching unit and a working circuit. The first clock unit is used for generating a first clock signal. The second clock unit is used for generating a second clock signal. The third clock unit is used for generating a third clock signal. The clock switching unit is used for receiving the first clock signal, the second clock signal and the third clock signal, selecting one of the first clock signal, the second clock signal and the third clock signal as a target clock signal and outputting the selected clock signal. The working circuit is used for working based on the current target clock signal output by the clock switching unit. The frequency of a system clock working in a low frequency state is gradually adjusted and improved to a target working frequency, thereby preventing the risk of overshoot of transient current of the system, and effectively ensuring the service life of a chip.