Low cost test vector compression/decompression scheme for circuits with a reconfigurable serial multiplier

TL;DR: Experimental results demonstrate that a high encoding efficiency can be achieved using the proposed test vector decompression scheme, which reduces hardware overhead by making use of existing functional circuitry.

Abstract: Many chip designs contain one or more serial multipliers. A scheme is proposed to exploit this to compress the amount of data that needs to be stored on the tester and transferred to the CUT during manufacturing test. The test vectors are stored on the tester in a compressed format by expressing each test vector as a product of two numbers. While performing multiplication on these stored seeds in the Galois field modulo 2, GF(2), the multiplier states (i.e. the partial products) are tapped to reproduce the test vectors and fill the scan chains. In contrast with other test vector decompression schemes that add significant test specific hardware to the chip, the proposed scheme reduces hardware overhead by making use of existing functional circuitry. Experimental results demonstrate that a high encoding efficiency can be achieved using the proposed scheme.