Journal Article10.1109/TVLSI.2011.2164951
Low-Complexity Reliability-Based Message-Passing Decoder Architectures for Non-Binary LDPC Codes
Xinmiao Zhang,Fang Cai,Shu Lin +2 more
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TL;DR: In this article, an iterative hard reliability-based majority-logic decoding (IHRB-MLGD) algorithm was proposed to achieve significant coding gain with small hardware overhead.
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Abstract: Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than their binary counterparts at the cost of higher decoding complexity when the codeword length is moderate. The recently developed iterative reliability-based majority-logic NB-LDPC decoding has better performance-complexity tradeoffs than previous algorithms. This paper first proposes enhancement schemes to the iterative hard reliability-based majority-logic decoding (IHRB-MLGD). Compared to the IHRB algorithm, our enhanced (E-)IHRB algorithm can achieve significant coding gain with small hardware overhead. Then low-complexity partial-parallel NB-LDPC decoder architectures are developed based on these two algorithms. Many existing NB-LDPC code construction methods lead to quasi-cyclic or cyclic codes. Both types of codes are considered in our design. Moreover, novel schemes are developed to keep a small proportion of messages in order to reduce the memory requirement without causing noticeable performance loss. In addition, a shift-message structure is proposed by using memories concatenated with variable node units to enable efficient partial-parallel decoding for cyclic NB-LDPC codes. Compared to previous designs based on the Min-max decoding algorithm, our proposed decoders have at least tens of times lower complexity with moderate coding gain loss.
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Citations
High-Throughput Efficient Non-Binary LDPC Decoder Based on the Simplified Min-Sum Algorithm
Xiaoheng Chen,Chung-Li Wang +1 more
TL;DR: A newly proposed simplified min-sum algorithm, which only has 0.05-0.1 dB performance loss against the sum-product algorithm, is developed, and a highly efficient decoder architecture is developed that increases the parallelism and throughput of the decoder by three to four times.
65
A High-Throughput Trellis-Based Layered Decoding Architecture for Non-Binary LDPC Codes Using Max-Log-QSPA
TL;DR: A high-throughput decoder architecture for non-binary low-density parity-check (LDPC) codes, where the QSPA in the log domain is considered, and an efficient trellis-based implementation can be used, where forward and backward recursions are involved.
46
A Fully Parallel Nonbinary LDPC Decoder With Fine-Grained Dynamic Clock Gating
TL;DR: This work presents a 1.22 Gb/s fully parallel decoder of a GF(64) (160, 80) regular-(2, 4) NB-LDPC code in 65 nm CMOS, and allows each processing node to detect its own convergence and apply dynamic clock gating to save power.
41
Bit-Reliability Based Low-Complexity Decoding Algorithms for Non-Binary LDPC Codes
TL;DR: In this article, the authors proposed bit-reliability based majority-logic decoding (MLgD) algorithms for non-binary LDPC codes, which pass only one Galois field element and its reliability along each edge of the Tanner graph.
37
Improved iterative soft-reliability-based majority-logic decoding algorithm for non-binary low-density parity-check codes
Chenrong Xiong,Zhiyuan Yan +1 more
- 01 Nov 2011
TL;DR: This paper proposes an improved ISRB majority-logic decoding algorithm by using a new reliability update, which achieves better error performance and faster convergence, while further reducing the computational complexity.
References
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Decoding Algorithms for Nonbinary LDPC Codes Over GF $(q)$
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Henk Wymeersch,Heidi Steendam,Marc Moeneclaey +2 more
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TL;DR: A log-domain decoding scheme for LDPC codes over GF(q) is introduced, which is mathematically equivalent to the conventional sum-product decoder but has advantages in terms of implementation, computational complexity and numerical stability.
Fast decoding algorithm for LDPC over GF(2/sup q/)
L. Barnault,David Declercq +1 more
- 04 Aug 2003
TL;DR: A modification of belief propagation is presented that enables us to decode LDPC codes defined on high order Galois fields with a complexity that scales as p log/sub 2/ (p), p being the field order.
299
An Efficient VLSI Architecture for Nonbinary LDPC Decoders
TL;DR: An efficient selective computation algorithm, which totally avoids the sorting process, is proposed for Min-Max decoding and an efficient VLSI architecture for a nonbinary Min- Max decoder is presented.
158