What is the overhead of the Residue CED scheme?

Other checkers, such as Checker 2 have only a 15% delay overhead over the direct DMR implementation and a 21% overhead over the unprotected version in the worst case.

How many times can the authors get yreal?

The authors obtain:yreal = 5•8 - 3•9 = 13 yimag = [(5+3)•(8+9)-(5-3)•(8-9)]/2=[8•17+2]/2 = 69 LHS = yreal+yimag = 13+69 = 82 RHS = (a+b)•(c+d)-2•(b•d) = 136-2•3•9 = 136-54 = 82

What are the two options for comparing with other error detection techniques?

To compare with other error detection techniques, Dual Modular Redundancy (DMR) and Concurrent Error Detection using residue codes were implemented.

How many real additions and 2 real comparisons?

Using the indirect implementation, in both the original and redundant modules, leads to an overall complexity of 6 real multiplications, 10 real additions and 2 real comparisons.

What is the CED architecture for DMR?

The use of reduced precision for the CED elements was also considered showing that it results in a different CED architecture providing the best results.

What was the reason why the DMR was not considered for reduced precision checking?

Concurrent error detection using residue codes does not allow for truncation and therefore these schemes were not considered for reduced precision checking.

What is the area of the reduced precision checker implementations?

The areas of the reduced precision checker implementations are reported in Table V. Checker 2 provides the lowest area with a reduction of 11% compared to the smallest DMR checker.

What is the way to evaluate the complexity of checkers?

To evaluate the circuit complexity and delay of checkers, they were implemented in VHDL and synthesized for the 45nm OSU FreePDK Standard Cell library [13] using Synopsys Design Compiler.

Open AccessJournal Article10.1109/TC.2012.246

Low Complexity Concurrent Error Detection for Complex Multiplication

Salvatore Pontarelli, +3 more

- 01 Sep 2013

- IEEE Transactions on Computers

- Vol. 62, Iss: 9, pp 1899-1903

TL;DR: This paper studies the problem of designing a low complexity Concurrent Error Detection (CED) circuit for the complex multiplication function commonly used in Digital Signal Processing circuits and proposes five novel CED architectures.

Abstract: This paper studies the problem of designing a low complexity Concurrent Error Detection (CED) circuit for the complex multiplication function commonly used in Digital Signal Processing circuits. Five novel CED architectures are proposed and their computational complexity, area, and delay evaluated in several circuit implementations. The most efficient architecture proposed reduces the number of gates required by up to 30 percent when compared with a conventional CED architecture based on Dual Modular Redundancy. Compared to a Residue Code CED scheme, the area of the proposed architectures is larger. However, for some of the proposed CEDs delay is significantly lower with reductions exceeding 30 percent in some configurations.

AI Agents for this Paper

Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps

Most frequently asked questions

1. What are the contributions in this paper?

This paper studies the problem of designing a low complexity Concurrent Error Detection ( CED ) circuit for the complex multiplication function commonly used in Digital Signal Processing circuits.

2. Why is a full analysis not included in the paper?

Since the objective is only to study how reduced precision affects the implementation complexity and speed of the different checkers, a full analysis is not included in the paper.

3. How did the Synopsys Design Compiler implement the parallel prefix structures?

1Synthesis was performed by configuring Synopsys Design Compiler to implement parallel prefix structures for the adders and multipliers.

4. How was the scheme applied to the direct and indirect implementations?

For residue codes, the scheme was applied by performing the modulo operation at the inputs and outputs of the complex multiplication such that both adders and multipliers are protected.

Figure 1. Direct implementation of complex multiplication.

Figure 2. Indirect implementation of complex multiplication.

Citations

Journal Article•10.1016/J.MICROREL.2015.08.017

Fault-tolerant carry look-ahead adder architectures robust to multiple simultaneous errors

Mojtaba Valinataj

- 01 Dec 2015

- Microelectronics Reliability

TL;DR: Analytical assessments show that, as well as correcting or detecting all single permanent or transient errors, multiple simultaneous errors in the new carry look-ahead adders are corrected or at least detected with a high probability independent of the number of errors.

...read moreread less

Journal Article•10.1016/J.MICPRO.2014.10.002

A novel self-checking carry lookahead adder with multiple error detection/correction

Mojtaba Valinataj

- 01 Nov 2014

- Microprocessors and Microsystems

TL;DR: A novel carry lookahead adder design is presented with multiple error detection/correction capability and it is analytically shown that this architecture has more reliability than the others, and the hardware implementation reveals thatThis architecture incurs much lower hardware overheads relative to traditional architectures while it provides higher error detection andcorrection efficiency.

...read moreread less

Journal Article•10.1016/J.MEJO.2018.08.014

A low-cost high-speed self-checking carry select adder with multiple-fault detection

Mojtaba Valinataj, +2 more

- 01 Nov 2018

- Microelectronics Journal

TL;DR: The carry select adder as one of the fastest adders is augmented respecting multiple-fault detection, delay, power and required area, and a new grouping structure for the self-checking multi-stage CSeA apart from the conventional square-root (SQRT) grouping is proposed to optimize the overall delay for different adder sizes.

...read moreread less

Journal Article•10.1109/TCAD.2015.2394389

Reliable Radix-4 Complex Division for Fault-Sensitive Applications

Mehran Mozaffari-Kermani, +2 more

- 21 Jan 2015

- IEEE Transactions on Computer-Aided Desi...

TL;DR: Different error detection architectures are proposed in this paper which can be tailored based on the eventual objectives of the designs in terms of area and time requirements, among which the schemes based on recomputations for different operands in addition to the unified parity (simplified detecting code) and hardware redundancy approach are presented.

...read moreread less

•Proceedings Article•10.5555/3145862.3145899

Automatic layout integration of bulk built-in current sensors for detection of soft errors

Mario Vinicius Guimaraes, +1 more

- 29 Aug 2016

TL;DR: The aim of this work is to present a methodology for automatic insertion of BBICS in common standard cell designs and demonstrate the feasibility of the approach and indicate requirements for future BBICS developments in order to reduce area offset.

...read moreread less

References

•Book

Discrete-Time Signal Processing

Alan V. Oppenheim, +1 more

- 01 Jan 1989

TL;DR: In this paper, the authors provide a thorough treatment of the fundamental theorems and properties of discrete-time linear systems, filtering, sampling, and discrete time Fourier analysis.

...read moreread less

11.8K

•Book

Discrete-time Signal Processing

Darrell Williamson

- 01 Jan 1999

4.5K

Journal Article•10.1109/MDT.2005.69

Soft errors in advanced computer systems

Robert Baumann

- 01 May 2005

- IEEE Design & Test of Computers

TL;DR: This article comprehensively analyzes soft-error sensitivity in modern systems and shows it to be application dependent.

...read moreread less

913

Proceedings Article•10.1109/MSE.2007.44

FreePDK: An Open-Source Variation-Aware Design Kit

James E. Stine, +10 more

- 03 Jun 2007

TL;DR: An open source, variation aware Process Design Kit (PDK), based on Scalable CMOS design rules, down to 45 nm, for use in VLSI research, education and small businesses is discussed.

...read moreread less

464

Journal Article•10.1109/TDMR.2005.855790

Design for soft error mitigation

Michael Nicolaidis

- 05 Dec 2005

- IEEE Transactions on Device and Material...

TL;DR: Various SEU and SET mitigation schemes that could help the designer meet her or his goals are described.

...read moreread less

351

...

Expand

Low Complexity Concurrent Error Detection for Complex Multiplication

Chat with Paper

AI Agents for this Paper

Most frequently asked questions

1. What are the contributions in this paper?

2. Why is a full analysis not included in the paper?

3. How did the Synopsys Design Compiler implement the parallel prefix structures?

4. How was the scheme applied to the direct and indirect implementations?

5. What is the overhead of the Residue CED scheme?

6. How many times can the authors get yreal?

7. What are the two options for comparing with other error detection techniques?

8. How many real additions and 2 real comparisons?

9. What is the CED architecture for DMR?

10. What was the reason why the DMR was not considered for reduced precision checking?

11. What is the area of the reduced precision checker implementations?

12. What is the way to evaluate the complexity of checkers?

Figures

Citations

Fault-tolerant carry look-ahead adder architectures robust to multiple simultaneous errors

A novel self-checking carry lookahead adder with multiple error detection/correction

A low-cost high-speed self-checking carry select adder with multiple-fault detection

Reliable Radix-4 Complex Division for Fault-Sensitive Applications

Automatic layout integration of bulk built-in current sensors for detection of soft errors

References

Discrete-Time Signal Processing

Discrete-time Signal Processing

Soft errors in advanced computer systems

FreePDK: An Open-Source Variation-Aware Design Kit

Design for soft error mitigation

Related Papers (5)

Quadruple Time Redundancy Adders

VLSI concurrent error correcting adders and multipliers

A VLSI Efficient Programmable Power-of-Two Scaler for $\{2^{n}-1,2^{n},2^{n}+1\}$ RNS

Efficient Online Self-Checking Modulo 2^n+1 Multiplier Design

A reconfigurable digital multiplier architecture