Proceedings Article10.1109/REAL.2002.1181567
Low-complexity algorithms for static cache locking in multitasking hard real-time systems
Isabelle Puaut,D. Decotigny +1 more
- 03 Dec 2002
- pp 114-123
177
TL;DR: This paper proposes two low-complexity algorithms for selecting the contents of statically-locked caches and evaluates their performances and compares them with those of a state of the art static cache analysis method.
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Abstract: Cache memories have been extensively used to bridge the gap between high speed processors and relatively slow main memories However, they are a source of predictability problems because of their dynamic and adaptive behavior and thus need special attention to be used in hard-real time systems A lot of progress has been achieved in the last ten years to statically predict the worst-case behavior of applications with respect to caches in order to determine safe and precise bounds on task worst-case execution times (WCETs) and cache-related preemption delays An alternative approach to cope with caches in real-time systems is to statically lock their contents such that memory access times and cache-related preemption times are predictable In this paper, we propose two low-complexity algorithms for selecting the contents of statically-locked caches We evaluate their performances and compare them with those of a state of the art static cache analysis method
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Citations
The worst-case execution-time problem—overview of methods and survey of tools
Reinhard Wilhelm,Jakob Engblom,Andreas Ermedahl,Niklas Holsti,Stephan Thesing,David Whalley,Guillem Bernat,Christian Ferdinand,Reinhold Heckmann,Tulika Mitra,Frank Mueller,Isabelle Puaut,Peter Puschner,Jan Staschulat,Per Stenström +14 more
TL;DR: Different approaches to the determination of upper bounds on execution times are described and several commercially available tools1 and research prototypes are surveyed.
Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems
Reinhard Wilhelm,Daniel Grund,Jan Reineke,Marc Schlickling,Markus Pister,Christian Ferdinand +5 more
TL;DR: The architectural influence on static timing analysis is described and recommendations as to profitable and unacceptable architectural features are given and results show that measurement-based methods still used in industry are not useful for quite commonly used complex processors.
Exploring locking & partitioning for predictable shared caches on multi-cores
Vivy Suhendra,Tulika Mitra +1 more
- 08 Jun 2008
TL;DR: This paper proposes the use of shared cache in a predictable manner through a combination of locking and partitioning mechanisms, revealing certain design principles that strongly dictate the performance of a predictable memory hierarchy.
Timing analysis of concurrent programs running on shared cache multi-cores
TL;DR: This paper develops a timing analysis method for concurrent software running on multi-cores with a shared instruction cache that progressively improves the lifetime estimates of tasks that execute concurrently on multiple cores, in order to estimate potential conflicts in the shared cache.
References
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
C. L. Liu,James W. Layland +1 more
TL;DR: The problem of multiprogram scheduling on a single processor is studied from the viewpoint of the characteristics peculiar to the program functions that need guaranteed service and it is shown that an optimum fixed priority scheduler possesses an upper bound to processor utilization.
Analysis of cache-related preemption delay in fixed-priority preemptive scheduling
Chang-Gun Lee,Hoosun Hahn,Yang-Min Seo,Sang Lyul Min,Rhan Ha,Seongsoo Hong,Chang Yun Park,Minsuk Lee,Chong Sang Kim +8 more
TL;DR: The results show that the proposed approach gives a prediction of the worst case cache-related preemption delay that is up to 60 percent tighter than those obtained from the previous approaches.
308
Guest Editorial: A Review of Worst-Case Execution-TimeAnalysis
Peter Puschner,Alan Burns +1 more
- 01 May 2000
TL;DR: The goal of this special issue is to review the achievements in WCET analysis and to report about the recent advances in this field.
271
Bounding pipeline and instruction cache performance
TL;DR: This paper describes an approach for bounding the worst and best case performance of large code segments on machines that exploit both pipelining and instruction caching and indicates that the timing analyzer efficiently produces tight predictions of best and best-case performance for pipelined and instruction cache.
Worst Case Execution Time Analysis for a Processor withBranch Prediction
Antoine Colin,Isabelle Puaut +1 more
- 01 May 2000
TL;DR: Experimental results show that the timing penalty due to wrong branch predictions estimated by the proposed technique is close to the real one, which demonstrates the practical applicability of the method.
207