Logic simulation machine

TL;DR: In this paper, an improved logic simulation machine is presented, in which non-unitary delays of logic functions being simulated are permitted and in which the delay time can be made different for low-to-high and high-tolow transitions.

Abstract: An improved logic simulation machine in which non-unitary delays of logic functions being simulated are permitted and in which the delay time can be made different for low-to-high and high-to-low transitions. A plurality of basic processors are interconnected with a control processor through an inter-processor switch. The logic functions being simulated are divided among the various basic processors. The control processor provides primary input data and communicates the results computed by the basic processors with other ones of the basic processors as needed. All of the basic processors and the control processor operate in variable length work cycles. The length of a work cycle is determined by a minimum work space value among all of the logic functions to be simulated, that is, a minimum time to a next successive transition in a simulated output among all of the simulated logic functions. Further, the presence of glitches in the simulated output is detected. The detected glitches are suppressed if their duration is less than the delay time of the logic function being simulated for a particular transition it is predicted to undergo.