LDPC check node implementation using reversible logic

TL;DR: This work proposes a low-power LDPC CN architecture using reversible logic gates, which achieves about 300% reduction in power delay product with affordable complexity as compared to its classical implementation.

Abstract: Reversible logic is an emerging digital design paradigm which promises low energy dissipation; thanks to its information-lossless nature. True potential of this exciting concept can only be assessed by facing the design of practical complexity applications. Low density parity check (LDPC) decoding is one such application from forward error correction domain. The core of LDPC decoding is the check node (CN) processor, which executes the decoding algorithm and constitutes a major portion of decoder's overall power consumption. This work proposes a low-power LDPC CN architecture using reversible logic gates. Transistor level design and full custom layout of proposed architecture is carried out on UMC 90 nm complementary metal–oxide–semiconductor technology. All reversible blocks of proposed CN are optimised for quantum cost, garbage outputs and transistor count. The CN functionality is validated with post-layout simulations, layout versus schematic checks and design rule checks. The proposed CN occupies a post-layout area of 0.013 mm2, achieves up to 4.3 GHz frequency and consumes 52 μ W power. The performance of proposed CN is also compared with its implementation using irreversible gates. The proposed CN achieves about 300% reduction in power delay product with affordable complexity as compared to its classical implementation.