Patent
ITLDD transistor having variable work function and method for fabricating the same
Scott S. Roth,Carlos A. Mazure,Kent J. Cooper,Wayne J. Ray,Michael P. Woo,Jung-Hui Lin +5 more
- 12 Oct 1990
53
TL;DR: In this paper, a semiconductor device and process wherein an ITLDD device is formed having an inverse-T (IT) transistor gate with a variable work function across the gate is attained by depositing a work function adjusting layer onto the thin gate extensions.
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Abstract: A semiconductor device and process wherein an ITLDD device (60) is formed having an inverse-T (IT) transistor gate with a variable work function (Φ) across the gate. The variable work function is attained by depositing a work function adjusting layer onto the thin gate extensions of the IT-gate. In accordance with one embodiment of the invention, a semiconductor substrate (10) of a first conductivity type is provided having a gate dielectric layer (12) formed thereon. First and second lightly doped regions (36, 37) of a second conductivity type are formed in the substrate which are spaced apart by a channel region (38). An IT-gate electrode (48) is formed on the gate dielectric layer overlying the first and second lightly doped regions and the channel region. The IT-gate has a relatively thick central section (32) and relatively thin lateral extensions (50) projecting from the central portion along the gate dielectric layer. A work function adjusting layer (46) overlies and is in intimate contact with at least the lateral extensions of the IT-gate. The presence of the work function adjusting layer changes the electrical characteristics of the extensions relative to the central section of the IT-gate. Heavily doped source and drain regions (52, 53) of the second conductivity type are formed in the substrate adjacent to the first and second lightly doped regions and aligned to the edge of the gate extensions.
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Citations
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References
Patent
Method for fabricating MOS transistors having gates with different work functions
James R. Pfiester
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TL;DR: In this paper, a process for forming an insulated gate field effect transistor (IGFET) with a semiconductor gate with a central portion and end portions on either side thereof where the portions are of two different conductivity types is described.
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Patent
Method of fabricating a LDDFET with self-aligned silicide
Fung-Ching Chao
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TL;DR: In this article, a method of fabricating a lightly-doped drain field effect transistor (LDDFET) with or without self-aligned silicide (salicide) on a substrate is disclosed.
118
Patent
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Takeshi Okazawa,Yoshiyuki Hirano +1 more
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TL;DR: A metal silicide film is formed on the sides of a polycrystalline silicon layer formed on a semiconductor substrate via an insulating film, and the surface of the metal silicides film is covered by a silicon oxide film, whereby the silicon layer has a low electrical resistance and no shortcircuiting is necessary as discussed by the authors.
110
A novel submicron LDD transistor with inverse-T gate structure
Tiao-Yuan Huang,W.W. Yao,R.A. Martin,A.G. Lewis,Mitsumasa Koyanagi,J.Y. Chen +5 more
- 01 Dec 1986
TL;DR: In this article, a novel inverse-T LDD (ITLDD) transistor is proposed, which features self alignments of n-LDD and n+source-drain implants to the inside and outside edge, respectively, of the IT gate structure.
93
Patent
Method for fabricating double implanted LDD transistor self-aligned with gate
Tiao-Yuan Huang
- 24 Nov 1989
TL;DR: An improved double implanted and aligned LDD transistor comprising a gate having a central alignment member and a pair of outboard alignment members having portions contiguous with the gate oxide layer is presented in this article.
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