Invalidation control method for instruction cache memory

TL;DR: In this paper, a first bus monitoring circuit monitoring the access of the first bus and nullifying an instruction code stored in the instruction cache memory on the main memory of a processor is proposed.

Abstract: PURPOSE:To make an effective use of the instruction cache memory and to prevent the efficiency of a processor from deteriorating by providing a first bus monitoring circuit monitoring the access of a first bus and nullifying an instruction code stored in the instruction cache memory on the instruction cache memory. CONSTITUTION:An. instruction cache memory 35 is composed of a mechanism controlling high-speed access storage device and cache so as to perform caching of the instruction code on a main memory 32 that a processor 31 refers to. A first bus monitoring circuit 37 monitors the access of a first bus 33, and nullifies an instruction code cached in an instruction cache memory 35 before rewriting when the instruction code cached in the instruction cache memory 35 are newly rewritten. Thus, the waiting time waiting for the instruction fetch for the instruction cache memory 35 can be reduced to the minimum. Moreover, the effect of the instruction cache memory will not be damaged since no purge is required.