International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

TL;DR: An architectural solution to building reliable on-chip memory in the future processor environment with negligible area and performance overhead is suggested and a decoupled yield model of compute cores and L2 caches in CMPs is developed, which shows that there will be many more L1 cache than compute cores in a chip.

TL;DR: This paper shows how, by using the powerful mechanism of transactions as a concurrency model, and by taking advantage of .NET introspection and attribute programming capabilities, this paper was able to develop a system-level modeling and parallel simulation environment.

TL;DR: Sequential 3D integration has been identified as a potential candidate for area efficient ICs and entails the sequential processing of tiers of devices, one on top of the other.

TL;DR: This paper presents an efficient integration of mutation analysis into CRV flows, not only as a coverage gauge for simulation adequacy but also, a step further, to direct a dynamic adjustment of the test probability distribution.

TL;DR: It is demonstrated that the metallic 1T phase of MoS2 can be locally induced on semiconducting 2H phase nanosheets, thus decreasing contact resistances to 200-300 Ω μm at zero gate bias.

TL;DR: This paper analyzes a PCM-based hybrid main memory system using an architecture level model of PCM and proposes simple organizational and management solutions of the hybrid memory that reduces the write traffic to PCM, boosting its lifetime from 3 years to 9.7 years.

TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.

TL;DR: The fabrication of nickel silicide/silicon (NiSi/Si) nanowire heterostructures with atomically sharp metal–semiconductor interfaces is demonstrated and field-effect transistors based on those heterostructure in which the source–drain contacts are defined by the metallic NiSi nanowires regions are produced.