International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

TL;DR: In this article, the authors discuss various aspects of research on materials for industrial applications, with emphasis on use of chalcogenides for optical fibers, electrochemical sensing, imaging and detection, biochemical sensing, data storage, photovoltaics and infrared detection.

TL;DR: Sensitivity evaluation discloses that the DP-DM-HTFET can be a promising candidate for CMOS-based label-free biosensing applications and nonuniform arrangement of biomolecules inside the cavity simulation has been done.

TL;DR: This paper presents a kernels-based architecture for sparse coding that can be applied to a neural sparse coding algorithm to give an O(N) reduction in energy for the entire algorithm when run with finite precision.

TL;DR: In this article, the authors studied the scattering effects in double-gate MOSFETs using Monte Carlo simulation and analyzed the nonequilibrium transport in the channel with the help of spectroscopy of the number of scatterings experienced by electrons.

TL;DR: It is demonstrated that the metallic 1T phase of MoS2 can be locally induced on semiconducting 2H phase nanosheets, thus decreasing contact resistances to 200-300 Ω μm at zero gate bias.

TL;DR: This paper analyzes a PCM-based hybrid main memory system using an architecture level model of PCM and proposes simple organizational and management solutions of the hybrid memory that reduces the write traffic to PCM, boosting its lifetime from 3 years to 9.7 years.

TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.

TL;DR: The fabrication of nickel silicide/silicon (NiSi/Si) nanowire heterostructures with atomically sharp metal–semiconductor interfaces is demonstrated and field-effect transistors based on those heterostructure in which the source–drain contacts are defined by the metallic NiSi nanowires regions are produced.