International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

TL;DR: It is found that @W-FinFET delivers better performance under irradiation as compared with conventional single gate MOS structures and Sentaurus simulation results obtained has been compared with the reported experimental data.

TL;DR: This paper describes the experiences of applying X.509-based certificates and public key infrastructures, VOMS, PERMIS, Kerberos and the Internet2 Shibboleth technologies for nanoCMOS security and outlines how these solutions are integrating to provide a complete end-to-end security framework meeting the demands of the nano CMOS electronics domain.

TL;DR: A very low cost design-for-diagnosis (DfD) solution for identifying faulty write drivers that consists in verifying logic and analog conditions that guarantee the fault-free behavior of the write driver.

TL;DR: In this article, the corner effect of Tri-gate bulk FinFETs is investigated by 3D process and device simulation and their electrical characteristics are compared for different bias conditions.

TL;DR: It is demonstrated that the metallic 1T phase of MoS2 can be locally induced on semiconducting 2H phase nanosheets, thus decreasing contact resistances to 200-300 Ω μm at zero gate bias.

TL;DR: This paper analyzes a PCM-based hybrid main memory system using an architecture level model of PCM and proposes simple organizational and management solutions of the hybrid memory that reduces the write traffic to PCM, boosting its lifetime from 3 years to 9.7 years.

TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.

TL;DR: The fabrication of nickel silicide/silicon (NiSi/Si) nanowire heterostructures with atomically sharp metal–semiconductor interfaces is demonstrated and field-effect transistors based on those heterostructure in which the source–drain contacts are defined by the metallic NiSi nanowires regions are produced.