International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

TL;DR: Locally generated, arbitrated clocks for GALS SoCs face the risk of synchronization failures if clock delays are not accounted for, based on clock delays, cycle times, and complexity of the asynchronous port controllers.

TL;DR: The ICV-SLID fabrication process is well suited for the cost-effective production of both, high-performance applications (e.g. 3D microprocessor) and highly miniaturized multi-functional systems as mentioned in this paper.

TL;DR: This work proposes a memristor crossbar circuit design paradigm in which memristors are modeled using the quantum mechanical phenomenon of tunneling and uses this circuit model to design and simulate various logic circuit designs capable of universal computation.

TL;DR: A redundant TSV architecture with reasonable cost is proposed in this paper and analysis on overall yield shows that the proposed design can successfully recover most of the failed chips and increase the yield of TSV to 99.4%.

TL;DR: It is demonstrated that the metallic 1T phase of MoS2 can be locally induced on semiconducting 2H phase nanosheets, thus decreasing contact resistances to 200-300 Ω μm at zero gate bias.

TL;DR: This paper analyzes a PCM-based hybrid main memory system using an architecture level model of PCM and proposes simple organizational and management solutions of the hybrid memory that reduces the write traffic to PCM, boosting its lifetime from 3 years to 9.7 years.

TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.

TL;DR: The fabrication of nickel silicide/silicon (NiSi/Si) nanowire heterostructures with atomically sharp metal–semiconductor interfaces is demonstrated and field-effect transistors based on those heterostructure in which the source–drain contacts are defined by the metallic NiSi nanowires regions are produced.