Interface between a microprocessor chip and peripheral subsystems

Patent

Interface between a microprocessor chip and peripheral subsystems

- 21 Dec 1978

158

TL;DR: In this article, an interface between a microprocessor chip and input/output, and memory modules is described, which uses a single, bidirectional bus comprised of a number of lines which is less than the number necessary to carry a complete address word or a full width data word.

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Citations

Patent

Integrated circuit I/O using a high performance bus interface

Michael Farmwald, +1 more

- 16 Apr 1991

TL;DR: In this article, the authors present a memory subsystem comprising at least two semiconductor devices (15, 16, 17), including at least one memory device connected to a bus (18), where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address.

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552

Patent

High performance, superscalar-based computer system with out-of-order instruction execution

Le Trong Nguyen, +8 more

- 05 Nov 2003

TL;DR: In this paper, a superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput is presented, where the data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

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275

Patent

Apparatus for synchronously generating clock signals in a data processing system

Michael Farmwald, +1 more

- 05 Mar 1992

TL;DR: In this paper, an apparatus for synchronously generating a first clock signal and a second clock signal in a second circuitry of a data processing system is described, where a clock generating circuitry generates a global clock signal.

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227

Patent

Protocol for communication with dynamic memory

Richard M. Barth, +5 more

- 18 Oct 1996

TL;DR: In this paper, a system and method for performing data transfers within a computer system is presented, which includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed.

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210

Patent

Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters

Thomas W. Craft, +2 more

- 30 Jun 1992

TL;DR: In this article, an arbitration system for a shared address, data and control bus provides burst mode operations for transferring data between a peripheral device and memory via a bus master, which is responsive to high priority bus activities such as memory refresh cycles and DMA cycles to temporarily transfer control of the shared bus from the bus master to a circuit controlling the high priority activity.

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200

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References

Patent

System and method for increasing microprocessor output data rate

Paul J. Cooper

- 23 Jun 1977

TL;DR: In this article, a system and method for a microprocessor having an eight-bit data bus and a sixteen-bit address bus is interconnected with a peripheral device to which a certain amount of data must be transferred at a data rate greater than is possible by utilizing the eight bit data bus to accomplish the transfer.

...read moreread less

63

Patent

Variable word width processor control

Roger Erwin Packard

- 28 Jun 1971

TL;DR: In this paper, a microprogrammed processor associated with a free field memory is described, in which operands of any length in terms of the number of bits can be processed.

...read moreread less

43

Patent

Digital data communications device with standard option connection

Arnold E. Adelman, +2 more

- 25 May 1978

TL;DR: In this paper, a communications device is used for transferring data to and from a data processing system, and a standard option connection is interposed between the controller and the signal source.

...read moreread less

32

Patent

Asynchronous bidirectional interface with priority bus monitoring among contending controllers and echo from a terminator

Thomas E. Alcorn, +1 more

- 20 Dec 1976

TL;DR: In this article, a bidirectional priority bus is provided interconnecting the channel with the controllers, each controller is assigned a priority level and each requesting controller gates a binary number corresponding to its priority level onto the common priority bus, if a controller detects a higher priority level than its own level on the bus it removes its priority number from the bus.

...read moreread less

31

Patent

Secondary storage facility with serial transfer of control messages

Roger E. Lawson

- 06 Jun 1977

TL;DR: In this paper, the authors present a controller-to-drive message transfer protocol for a secondary storage facility that includes a controller and a drive bus that interconnects the controller and drive, where data is transferred between the drive and controller in serial fashion over a read/write data line.

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