Patent
Interconnect structure comprising semiconductor material
Niuya Takayuki,Ming Yang +1 more
- 08 Oct 1997
TL;DR: An interconnect for a semiconductor device, comprising: a first region 304 over a substrate 300, said first region having a first resistivity; a second region 306 over said first Region, said second region having lower resistivity than said firstRegion; and a third region 308 over said second Region,said third Region having a higher resistivities than said secondRegion, is discussed in this article.
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Abstract: An interconnect for a semiconductor device, comprising: a
first region 304 over a substrate 300, said first region having
a first resistivity; a second region 306 over said first region,
said second region having a lower resistivity than said first
region; and a third region 308 over said second region, said
third region having a higher resistivity than said second
region. The first region is preferably a layer of polysilicon
deposited over a gate oxide layer 302. The second region is a
silicide, such as tungsten disilicide, and the third region is
preferably polysilicon.
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References
Patent
Process for fabricating a control gate for a floating gate FET
Hsingya Arthur Wang
- 29 Nov 1989
TL;DR: In this paper, a multi-layer control gate line with a first polysilicon layer, a silicide layer, and a second poly-silicide layer is constructed using a single pump-down operation.
62
Patent
Method for fabricating polycide gate MOSFET devices
Ancheor Chen,Gary Hong +1 more
- 22 May 1995
TL;DR: In this paper, a method of fabricating MOSFET device with polycide gate, which includes a polysilicon layer and a refractory metal silicide layer, is described.
56
Patent
Semiconductor device and a method of fabricating the same
Toyokazu Fujii,Yasushi Naito +1 more
- 11 Dec 1992
TL;DR: In this paper, a polycide interconnection is connected to the p-type impurity diffused region in a semiconductor device, which includes a polysilicon substrate, a refractory metal silicide film, and a poly-silicon film.
25
Patent
Method of producing stable, low ohmic contacts in integrated semiconductor circuits
Dietrich Widmann,Reiner Sigusch +1 more
- 24 Apr 1984
TL;DR: In this paper, a method for producing stable, low resistance contacts in integrated semiconductor circuits consisting of aluminum or aluminum alloy outer contact conductor path planes is proposed, where the reliability and capacity of electrical conductor tracks is increased for VLSI systems.
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