Interconnect-Based Design Methodologies for Three-Dimensional

TL;DR: In this article, a 3-D NoC topology for a 180 nm silicon-on-insulator (SOI) technology is presented, and a 3D test circuit fabricated with the SOI technology is described.

Abstract: Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides achieved in 3-D manu- facturing technologies. Advanced design methodologies for two-dimensionalcircuits are notsufficienttomanagetheadded complexity caused by the third dimension. Consequently, design methodologies that efficiently handle the added com- plexityandinherentheterogeneityof3-Dcircuitsarenecessary. These 3-D design methodologies should support robust and reliable3-Dcircuitswhileconsideringdifferentformsofvertical integration, such as system-in-package and 3-D ICs with fine grain vertical interconnections. Global signaling issues, such as clock and power distribution networks, are further exacerbated in vertical integration due to the limited number of package pins, the distance of these pins from other planes within the 3-D system, and the impedance characteristics of the through silicon vias (TSVs). In addition to these dedicated networks, global signaling techniques that incorporate the diverse traits of complex 3-D systems are required. One possible approach, potentially significantly reducing the complexity of intercon- nectissuesin 3-Dcircuits,is3-Dnetworks-on-chip(NoC).Design methodologies that exploit the diversity of 3-D structures to further enhance the performance of multiplane integrated systems are necessary. The longest interconnects within a 3-D circuit are those interconnects comprising several TSVs and traversing multiple physical planes. Consequently, minimizing the delay of the interplane nets is of great importance. By considering the nonuniform impedance characteristics of the interplane interconnects while placing the TSVs, the delay of these nets is decreased. In addition, the difference in electrical behavior between the horizontal and vertical interconnects suggests that asymmetric structures can be useful candidates for distributing the clock signal within a 3-D circuit. A 3-D test circuit fabricated with a 180 nm silicon-on-insulator (SOI) technology, manufactured by MIT Lincoln Laboratories, explor- ing several clock distribution topologies is described. Correct operation at 1 GHz has been demonstrated. Several 3-D NoC topologies incorporating dissimilar 3-D interconnect structures arereviewedasapromisingsolutionforcommunicationlimited systems-on-chip (SoC). Appropriate performance models are described to evaluate these topologies. Several forms of vertical integration, such as system-in-package and different candidate technologies for 3-D circuits, such as SOI, are considered. The techniques described in this paper address fundamental interconnect structures in the 3-D design process. Several interesting research problems in the design of 3-D circuits are also discussed.