Integrated encoder decoder for variable length, zero run length limited codes

TL;DR: In this article, an encoder-decoder apparatus was described for encoding and decoding code words of a predetermined code scheme in which ONE bits thereof are separated by at least d zero bits and not more than k zero bits, in a serial bit stream path from and to components of serial data words each being of n parallel data bits in a data word transmission path.

Abstract: An encoder-decoder apparatus is disclosed for encoding and decoding code words of a predetermined code scheme in which which ONE bits thereof are separated by at least d ZERO bits and not more than k ZERO bits, in a serial bit stream path from and to components of serial data words each being of n parallel data bits in a data word transmission path, wherein the number of bits of each code word bears a three to two relation with respect to the number of bits of each component of the data word, and where n equals an even integer. The encoder-decoder includes an encode/decode clocked shift register connected to the serial bit stream path for receiving and framing each incoming code word and for putting out each framed incoming code word in parallel bit format, and for receiving each outgoing code word in parallel bit format and for putting out each outgoing code word into the serial bit stream path; an encode/decode serializing and deserializing shift register latch connected to the data word transmission path for receiving and latching each data word coming in from, and for receiving and latching each present data word going out to, the data word transmission path; an encoder for encoding, and a decoder for decoding. The serializing and deserializing shift register latch is clocked at a first rate corresponding to the latching of each incoming and outgoing data word of n bit length and a second rate by which the shift register latch is shifted by the number of bits of the data word component.