Integrated circuits for testing a display array

TL;DR: In this article, an improved apparatus for testing an array of pixel cells formed on a substrate is provided, in which each pixel cell is coupled to at least one gate line of a plurality of gate lines formed on the substrate and at least two data lines of the plurality of data lines formed in the substrate.

Abstract: An improved apparatus for testing an array of pixel cells formed on a substrate is provided. Each pixel cell is coupled to at least one gate line of a plurality of gate lines formed on the substrate and at least one data line of a plurality of data lines formed on the substrate. The gate lines and/or data lines are partitioned into a plurality of groups. For each particular group, a first probe pad and select logic is formed on said substrate. The select logic, which is coupled between the first probe pad and the lines of the particular group, selectively couples the first probe pad to the lines of said particular group based upon first control signals supplied to the select logic during a test routine whereby charge is written to, stored, and read from the array of pixel cells. In addition, a second probe pad and hold logic for each particular group may be formed on the substrate. The hold logic, which is coupled between the second probe pad and the lines of the particular group, selectively couples the second probe pad to the lines of the particular group based upon second control signals supplied to the hold logic during the test routine. The apparatus provides a flexible interface between the array under test and the test system, which minimizes the redesign costs when the size and/or resolution of the array under test is varied.