Patent
Integrated circuit memory devices having error checking and correction circuits therein and methods of operating same
Jung-Bae Lee
- 07 Aug 2000
22
TL;DR: In this article, an error check circuit is provided that converts the stored data bits and the parity bits into a plurality of syndrome bits (e.g., Si) that designate a location of a bit error in the storage data bits when compared against the original write data bits.
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Abstract: Integrated circuit memory devices include a memory cell array having therein a plurality of stored data bits and a plurality of parity bits generated from a plurality of write data bits received by the memory device during a write operation. The plurality of stored data bits and the plurality of parity bits may collectively form a word having a length of m+p bits, where m and p are integers. An error check circuit is provided that converts the plurality of stored data bits and the plurality of parity bits into a plurality of syndrome bits (e.g., Si) that designate a location of a bit error in the plurality of stored data bits when compared against the original write data bits. An error correction circuit is provided that uses the plurality of syndrome bits to correct an error in the plurality of stored data bits and generate a plurality of read data bits that match the plurality of original write data bits.
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Citations
Patent
Integrated circuit having memory array including ECC and column redundancy and method of operating same
Anant Pratap Singh
- 29 Nov 2011
TL;DR: In this article, an integrated circuit device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns, coupled with multiplexer circuitry coupled to the memory cell arrays, comprising a data multiplexers, each data multiplerixer having a multiplicity of inputs, comprising (i) a first input to receive write data which is representative of data to be written into the memory cells of the memory array in response to a write operation, and (ii) a second input to receiving read data which are representative of read data read from memory cells
137
Patent
Digit line comparison circuits
Dean A. Klein
- 16 Feb 2011
TL;DR: In this article, the memory cells that are unable to retain data bits are identified by a modified sense amplifier and a refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells.
135
Patent
Semiconductor memory device.
Tomoharu Tanaka,Hiroshi Nakamura,Toru Tanzawa +2 more
- 12 Mar 2008
TL;DR: In this paper, the read circuit senses a change in a voltage of the bitline of a bitline, and applies a voltage which is different from the first voltage to the gate of the first transistor when it senses a voltage change.
119
Patent
Memory system and method having selective ECC during low power refresh
Dean A. Klein
- 11 May 2006
TL;DR: In this article, a processor switches the DRAM to a low power refresh mode, in which DRAM cells are refreshed at a sufficiently low rate that data retention errors may occur.
104
Patent
Memory system and method using ECC to achieve low power refresh
Dean A. Klein,John F. Schreck +1 more
- 28 Jul 2005
TL;DR: In this paper, the data from the rows of memory cells are read, and the stored syndromes are used to determine if there are errors in the read data and correct any errors that are found.
80
References
A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC
Howard Leo Kalter,C.H. Stapper,John E. Barth,J. Dilorenzo,Charles Edward Drake,John A. Fifield,Gordon Arthur Kelley,Scott C. Lewis,W.B. van der Hoeven,James Andrew Yankosky +9 more
TL;DR: A high-speed 16-Mb DRAM chip with on-chip error-correcting code (ECC), which supports either 11/11 or 12/0 RAS/CAS addressing and operates on a 3.3- or 5-V power supply, is described.
184
Patent
Storage device array architecture with solid-state redundancy unit
David W. Gordon
- 14 Oct 1994
TL;DR: In this paper, the authors proposed a fault-tolerant storage device array using a solid-state storage unit for storage of redundancy information, which solves the redundancy bottleneck inherent in a RAID 4 architecture by replacing the electro-mechanical redundancy storage unit with a solid state device (SSD).
107
Patent
Fault mapping apparatus for memory
Shanker Singh
- 07 Jan 1991
TL;DR: The SEC/DED syndrome generator as discussed by the authors detects single and double bit errors, correcting the single bit errors while providing an indication of which memory generated the error, by grouping the memories and testing only the memories in that group.
86
Patent
Dram on-chip error correction/detection
Michael B. Raynham
- 13 Feb 1990
TL;DR: In this paper, error detection and correction are performed on the same chip as DRAM memory, where the data and error correction bits need not travel on an external bus, and error detection/correction can be conducted on a larger number of bits than the width of the data bus.
86
Patent
Multi-bit memory device having error check and correction circuit and method for checking and correcting data errors therein
Byeng-Sun Choi
- 18 Dec 1998
TL;DR: An integrated circuit multi-bit memory device incorporating an error check and correction (ECC) technique is provided in this paper, where two or more groups of parity bits corresponding to a data word of the memory device are programmed therein.
84