Patent
Integrated circuit having memory array including ECC and column redundancy and method of operating same
Anant Pratap Singh
- 29 Nov 2011
137
TL;DR: In this article, an integrated circuit device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns, coupled with multiplexer circuitry coupled to the memory cell arrays, comprising a data multiplexers, each data multiplerixer having a multiplicity of inputs, comprising (i) a first input to receive write data which is representative of data to be written into the memory cells of the memory array in response to a write operation, and (ii) a second input to receiving read data which are representative of read data read from memory cells
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Abstract: An integrated circuit device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns; multiplexer circuitry, coupled to the memory cell array, comprising a plurality of data multiplexers, each data multiplexer having a plurality of inputs, comprising (i) a first input to receive write data which is representative of data to be written into the memory cells of the memory cell array in response to a write operation, and (ii) a second input to receive read data which is representative of data read from memory cells of the memory cell array, and an associated output to responsively output data from one of the plurality of inputs; and syndrome generation circuitry, coupled to the multiplexer circuitry, to generate: (i) a write data syndrome vector using the write data and (ii) a read data syndrome vector using the read data.
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Citations
Patent
Apparatuses and methods for performing logical operations using sensing circuitry
Troy A. Manning
- 04 Jun 2015
TL;DR: In this paper, the authors present an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array, which can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, and perform a number of intermediate operation phases of the logical operation.
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Troy A. Manning
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TL;DR: In this paper, the authors present apparatuses and methods related to performing compare and/or report operations using sensing circuitry, such as charging an input/output (IO) line of a memory array to a voltage.
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- 04 Nov 2014
TL;DR: In this article, the present disclosure provides apparatuses and methods for performing division operations in a memory, including a first address space comprising a first number of memory cells coupled to a sense line and to a second number of select lines wherein the second address space stores a divisor value.
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Troy A. Manning
- 30 Aug 2013
TL;DR: In this article, the authors present devices and methods for accessing a memory array address space, including a first address space comprising memory cells coupled to a first number of select lines and to a number of sense lines, and a second address space consisting memory cells coupling to a second number of selected lines and the number of senses.
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TL;DR: In this article, apparatuses and methods related to identifying an extremum value using sensing circuitry are described, including methods for determining the value of the extremum by reading memory cells coupled to the sense line.
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