Patent
Integrated circuit device
Hang-Ting Lue
- 04 Feb 2015
TL;DR: In this paper, an integrated circuit (IC) is defined as a memory array with plural bit lines coupled with corresponding columns of memory cells in the array, plural reference lines, a plurality of access gate word lines coupled to access gates in corresponding rows in an array, and a memory gate word line coupled to memory gates in respective rows in corresponding arrays.
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Abstract: An integrated circuit device, based on this architecture comprises a memory array with plural bit lines coupled with corresponding columns of memory cells in the array, plural reference lines, a plurality of access gate word lines coupled to access gates in corresponding rows in the array and a plurality of memory gate word lines coupled to memory gates in corresponding rows in the array. The memory cells in the array include respective access transistors having access gates and memory transistors having memory gates arranged in series between the corresponding bit lines and one of the plural reference lines. A memory transistor in a memory cell comprises a semiconductor body including a channel having a channel surface and a charge storing dielectric stack between the memory gate and the channel surface. The dielectric lamination layer comprises a tunneling dielectric layer connected with one of the memory gate and the channel surface and a blocking dielectric layer, and the dielectric lamination layer also comprises an electric charge trapping dielectric layer arrange on the tunneling dielectric layer.
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References
Patent
Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays
Szu Yu Wang,Hang-Ting Lue +1 more
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TL;DR: In this paper, memory cells comprising a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region are described along with arrays thereof and methods of operation.
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Charge trapping devices with field distribution layer over tunneling barrier
Hang-Ting Lue
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TL;DR: In this paper, a memory cell comprising a semiconductor substrate with a surface with a source region and a drain region disposed below the surface of the substrate and separated by a channel region is described.
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Patent
Non-volatile memory and manufacturing method thereof
Tung-Po Chen
- 28 Mar 2005
TL;DR: In this paper, a method of manufacturing nonvolatile memory is described, in which a substrate is provided and a plurality of stacked gate structures is formed on the substrate, each stacked gate structure includes a tunneling dielectric layer, a floating gate, a first inter-gate dielectrics layer, control gate and a cap layer.
13