Patent
Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
Kent L. Gilson
- 11 Dec 1992
346
TL;DR: In this article, an integrated circuit computing device is comprised of a dynamically configurable Field Programmable Gate Array (FPGA), which is configured to implement a RISC processor and a Reconfigurable Instruction Execution Unit.
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Abstract: An integrated circuit computing device is comprised of a dynamically configurable Field Programmable Gate Array (FPGA). This gate array is configured to implement a RISC processor and a Reconfigurable Instruction Execution Unit. Since the FPGA can be dynamically reconfigured, the Reconfigurable Instruction Execution Unit can be dynamically changed to implement complex operations in hardware rather than in time-consuming software routines. This feature allows the computing device to operate at speeds that are orders of magnitude greater than traditional RISC or CISC counterparts. In addition, the programmability of the computing device makes it very flexible and hence, ideally suited to handle a large number of very complex and different applications.
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Citations
Patent
Automated processor generation system for designing a configurable processor and method for the same
Earl A. Killian,Ricardo E. Gonzalez,Ashish B. Dixit,Monica S. Lam,Walter D. Lichtenstein,Christopher Rowen,John C. Ruttenberg,Robert P. Wilson,Albert Wang,Dror E. Maydan +9 more
- 15 Feb 2001
TL;DR: In this article, an automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it.
551
Patent
Methods and apparatus for control using control devices that provide a virtual machine environment and that communicate via an ip network
Alexander Johnson,Paul C. Badavas,T. Eric Christiansen,Peter D. Hansen,Thomas B. Kinney,Seyamak Keyghobad,Bo Ling,Richard L. Thibault +7 more
- 20 Jul 2007
TL;DR: In this article, the authors describe a virtual machine for control using field and control devices that provide a virtual environment and communicate via an IP network. But their work is limited to the control of a single field device.
378
Patent
Methods and apparatus for control configuration with versioning, security, composite blocks, edit selection, object swapping, formulaic values and other aspects
Keith Eldridge,Paul Meskonis,Robert Hall,Kenneth A. Burke,Scott Volk,Mark Johnson,Brian Mackay,Steven Dardinski +7 more
- 17 May 2000
318
Patent
Process control configuration system with connection validation and configuration
Steven Dardinski,Keith Eldridge,Robert Hall,Mark Johnson,Brian Mackay,Paul Meskonis,Scott Volk +6 more
- 14 Feb 2006
TL;DR: In this article, a set of data structures (e.g., the object connection type structures) identify valid types for component-to-component pairings and the respective roles of each component in the pairing.
294
Patent
Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
Paul L. Master,Eugene Hogenauer,Walter James Scheuermann +2 more
- 11 Mar 2002
TL;DR: In this article, a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing is proposed, which includes a plurality of heterogeneous computational elements coupled to an interconnection network.
256
References
Patent
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Ross H. Freeman
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TL;DR: In this article, a configurable logic array is defined as a plurality of logic elements that can be configured to perform different logic functions depending upon the control information placed in each logic element.
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Patent
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Hung-Cheng Hsieh,W.S. Carter,J.Y. Ja,Edmond Y. Cheung,S. Schreifels,Charles R. Erickson,P. Freidin,L.G. Tinkey,R. Kanazawa +8 more
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TL;DR: Using a combination of architectural and process improvements, a third-generation family of field-programmable gate arrays (FPGAs) features up to twice the density and speed of currently-available FPGA devices.
156
Patent
Logic block for programmable logic devices
Randy Charles Steele
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TL;DR: In this paper, a standard logic block, or macrocell, is provided for use on programmable logic devices, which uses RAM to perform logic functions, and further includes circuitry which allows writing of data to the RAM during use.
141
Patent
Programmable logic array having a changeable logic structure
Harufusa Kondou,Hiroshi Kuranaga +1 more
- 10 Nov 1988
TL;DR: In this article, a Programmable Logic Array (PLA) cells are arranged at intersections of input lines and output lines of the array and switches for programming the PLA cells to implement a desired logic function are controlled by data stored in a random access memory whereby programming of the PLA can be changed arbitrarily and during operation of a system including the PLA.
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