Open Access
Instruction sets mixed-width
Arvind Krishnaswamy,Rajiv Gupta +1 more
- 01 Jan 2003
About: The article was published on 01 Jan 2003. and is currently open access. The article focuses on the topics: Instruction set.
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Citations
Simple offset assignment in presence of subword data
Bengu Li,Rajiv Gupta +1 more
- 30 Oct 2003
TL;DR: This work introduces the SubWord Offset Assignment (SWOA) problem and solves it using a Path Cover with Node Coalescing (PCwNC) formulation, and presents three heuristics to solve the PCwNC problem.
15
Power-adaptive microarchitecture and compiler design for mobile computing
Rajiv Gupta,Santosh Pande,Soner Önder +2 more
- 01 Jan 2003
TL;DR: Low power data caches and low power external data buses are designed that can be used for both superscalar and embedded processors and techniques for lowering the power consumption without significant sacrifice in performance are developed.
References
A 160 MHz 32 b 0.5 W CMOS RISC microprocessor
J. Montanaro,R. Witek,K. Anne,A.J. Black,Elizabeth M. Cooper,Daniel W. Dobberpuhl,P. Donahue,J. Eno,A. Farell,G. Hoeppner,D. Kruckemyer,Thomas H. Lee,P. Lin,L. Madden,Daniel C. Murray,M. Pearce,S. Santhanam,K. Snyder,R. Stephany,S.C. Thierauf +19 more
- 08 Feb 1996
TL;DR: This custom VLSI implementation of a microprocessor architecture delivers 184 Drystone/MIPS at 162 MHz dissipating 0.5 W using an 1.5 V internal supply and Clock generation uses an on-chip PLL with 3.68 MHz input clock to minimize high frequency clock signals on the board.
733
An Integrated Cache Timing and Power Model
Glen Reinman,Norman P. Jouppi,Glenn Reinman,Norm Jouppi +3 more
- 01 Jan 2002
TL;DR: CACTI uses an analytical model to estimate delay down both tag and data paths to determine the best configuration for a given cache size, block size, and associativity (at 0:80 m technology size).
Profile guided selection of ARM and thumb instructions
Arvind Krishnaswamy,Rajiv Gupta +1 more
- 19 Jun 2002
TL;DR: While Thumb code may be smaller than ARM code, it may perform poorly and thus may not lead to overall energy savings, and thus the energy consumed by the I-cache, can be reduced.
The SimpleScalar tool set, version 2.0
Doug Burger,Todd Austin +1 more
TL;DR: This document describes release 2.0 of the SimpleScalar tool set, a suite of free, publicly available simulation tools that offer both detailed and high-performance simulation of modern microprocessors.