Open Access
Instruction-Level Execution Migration
Srinivas Devadas,Mieszko Lis,Omer Khan +2 more
- 17 Apr 2010
TL;DR: To evaluate the potential of EM 2 architectures, a series of PIN/Graite-based models of an EM 2 multicore with 64 x86 cores were developed and, under some simplifying assumptions, they were compared against corresponding directory -based cache -coherent architecture models.
read more
Abstract: NWe introduce the Execution Migration Machine (EM 2 ), a novel data -centric multicore memory system architectu re based on computation migration. Unlike traditional distributed memory multicores, which rely on complex cache coherence protocols to move the data to the core where the computation is taking place, our scheme always moves the computation to the core whe re the data resides. By doing away with the cache coherence protocol, we are able to boost the effectiveness of per-core caches while drastically reducing hardware complexity. To evaluate the potential of EM 2 architectures, we developed a series of PIN/Gra phite-based models of an EM 2 multicore with 64 x86 cores and, under some simplifying assumptions (a timing model restricted to data memory performance, no instruction cache modeling, high -bandwidth fixed -latency interconnect allowing concurrent migrations) , compared them against corresponding directory -based cache -coherent architecture models. We justify our assumptions and show that our conclusions are valid even if our assumptions are removed. Experimental results on a range of SPLASH -2 and PARSEC benchma rks indicate that EM
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
References
The SPLASH-2 programs: characterization and methodological considerations
Steven Cameron Woo,Moriyoshi Ohara,Evan Torrie,Jaswinder Pal Singh,Anoop Gupta +4 more
- 01 May 1995
TL;DR: This paper quantitatively characterize the SPLASH-2 programs in terms of fundamental properties and architectural interactions that are important to understand them well, including the computational load balance, communication to computation ratio and traffic needs, important working set sizes, and issues related to spatial locality.
The PARSEC benchmark suite: characterization and architectural implications
Christian Bienia,Sanjeev Kumar,Jaswinder Pal Singh,Kai Li +3 more
- 25 Oct 2008
TL;DR: This paper presents and characterizes the Princeton Application Repository for Shared-Memory Computers (PARSEC), a benchmark suite for studies of Chip-Multiprocessors (CMPs), and shows that the benchmark suite covers a wide spectrum of working sets, locality, data sharing, synchronization and off-chip traffic.
Thousand core chips: a technology perspective
Shekhar Borkar
- 04 Jun 2007
TL;DR: The many-core architecture, with hundreds to thousands of small cores, is presented to deliver unprecedented compute performance in an affordable power envelope and fine grain power management, memory bandwidth, on die networks, and system resiliency are discussed.
1K
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS
Sriram R. Vangal,Jason Howard,Greg Ruhl,Saurabh Dighe,H. Wilson,James W. Tschanz,D. Finan,A. Singh,Tiju Jacob,Shailendra Jain,Vasantha Erraguntla,Clark Roberts,Yatin Hoskote,Nitin Borkar,Shekhar Borkar +14 more
TL;DR: In this paper, an integrated network-on-chip architecture containing 80 tiles arranged as an 8x10 2D array of floating-point cores and packet-switched routers, both designed to operate at 4 GHz.
740
TILE64 - Processor: A 64-Core SoC with Mesh Interconnect
Shane L. Bell,Bruce S. Edwards,John Amann,Richard Conlin,Kevin Joyce,V. Leung,J. MacKay,M. Reif,Liewei Bao,J.F. Brown,Matthew Mattina,Chyi-Chang Miao,Carl Ramey,David Wentzlaff,W. Anderson,E. Berger,N. Fairbanks,D. Khan,F. Montenegro,J. Stickney,J. Zook +20 more
- 01 Feb 2008
TL;DR: The TILE64TM processor is a multicore SoC targeting the high-performance demands of a wide range of embedded applications across networking and digital multimedia applications.
696
Related Papers (5)
Mark D. Hill,Michael R. Marty +1 more
- 01 Jan 2008
Tong Chen,Haibo Lin,Tao Zhang +2 more
- 07 Jun 2008