Patent
Input/output interface bus apparatus
Donall G. Bourke,Dagurasu Roderitsuku Chizamu,Guregorii Deiru Furooto,Richiyaado Aren Kerii,Roi Yoanin Riyuu,Kaaru Arubaato Marumukuisuto,John M. Nelson,Chiyaaruzu Baatoran Paakinzu J,Richiyaado Raian Pureisu,Haatomuuto Roberuto Shiyuwaeim,Jiyon Deibuitsudo Uiruson +10 more
- 20 Apr 1988
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TL;DR: In this article, the authors propose a data processing system in which an input output interface controller (IOIC) is connected to a storage controller (SC) via a synchronous bus.
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Abstract: In a data processing system, an input output bus unit (IOBU) is connected to one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous "handshaking" manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, and SC/IOIU, such as a unit operation, a storage operation, and a message acceptance operation.
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Citations
Patent
Personal computer system
Danieru Pooru Fuotsuko,Ruisu Antonio Herunandesu,Eritsuku Mateisen,Denisu Rii Miyuraa,Jiyonasan Henrii Reimondo,Esumairu Tashiyakori +5 more
- 23 Apr 1993
TL;DR: In this article, the authors present a personal computer system for restoring and controlling a processor which is has been already reset, initialized, and separated when an alternative system controller is present in the system.
References
Patent
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TL;DR: In this article, the authors propose to enable either one of the synchronous and nonsynchronous data transfer between the channel device of the circuit control and the line adaptor by giving the function to transmit the service-in signal to the line adapator.
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Patent
Multiple data processing system
Mori Riyuuichi,Shiraoka Sachio +1 more
- 16 Sep 1977
TL;DR: In this paper, the authors propose a multiple data processing device in which a local memory control device controlling a LMC and a CPU are synchronous, and a common memory controller device accessing the common memory device accessed by the respective CPU is asynchronous with the local MC and the CPU.
4
Patent
Data transfer controller
Awaji Toshio,Hishinuma Chiaki,Miki Shiyuuji,Kajizuka Shiyouji,Seo Tomihide,Dewa Hiroshi +5 more
- 12 Apr 1982
TL;DR: In this article, the authors proposed to increase the data transfer speed by operating both buses in parallel, when controlling a data transfer of a processor group coupled with a high-speed bus, and a processor groups coupled with low speed bus.
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