Patent
Input interface circuit
Obata Hiroyuki,Takagi Tomokazu +1 more
- 14 Jan 2010
TL;DR: In this paper, the authors proposed an inexpensive input interface circuit that prevents a malfunction in a simple configuration even at an input signal voltage lower than a power supply potential, where the gate terminal G connected in common is used as an input terminal.
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Abstract: PROBLEM TO BE SOLVED: To provide an inexpensive input interface circuit that prevents a malfunction in a simple configuration even at an input signal voltage lower than a power supply potential. SOLUTION: The input interface circuit I10 includes a CMOS inverter C10 configured by connecting a P-channel MOS transistor M1 and an N-channel MOS transistor M2 in series and connecting a gate terminal G to both transistors in common. The gate terminal G connected in common is used as an input terminal. A semiconductor element S10 having a threshold voltage and the CMOS inverter C10 are connected in series between a power supply terminal and a ground terminal. A resistor R10 and a second N-channel MOS transistor M3 are connected in series between the power supply terminal and the ground terminal. A gate terminal G of the second N-channel MOS transistor M3 is connected to a series connection point P1. An output is taken out from a series connection point P2. COPYRIGHT: (C)2011,JPO&INPIT
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References
Patent
Semiconductor inputting circuit
Shitei Tsunaaki
- 26 Sep 1983
TL;DR: In this article, the authors proposed to suppress influence of variation of manufacture to minimum by a titled semiconductor inputting circuit, by forming said circuit by an input level converting circuit block and a bistable state holding circuit block, and eliminating DC power consumption by the whole input-level circuit.
5
Patent
Semiconductor integrated circuit
Owada Masakatsu
- 28 Nov 1997
TL;DR: In this paper, the power voltage of input inverter circuits Q11 to Q14 consisting of complementary MOS transistors TR are set at a voltage level that is decided by adding the threshold voltage of the P-channel MOS TR Q11 which is generated by a threshold voltage generation circuit 28 to the voltage VO of the least standard value of the input logical high level of a semiconductor integrated circuit.
2
Patent
Ttl level input buffer circuit
Kashimura Masahiko
- 10 Dec 1993
TL;DR: In this article, three MOSFETs are connected in series between a power supply 6 and an earth 7, and the gate electrodes of the gate terminals serve as the input terminals IN respectively.
1