Input buffer circuit

TL;DR: In this article, the problem of providing an input buffer circuit that eliminates an output signal distortion by suppressing a logic threshold voltage variation due to process variations of MOS transistors is addressed.

Abstract: PROBLEM TO BE SOLVED: To provide an input buffer circuit that eliminates an output signal distortion by suppressing a logic threshold voltage variation due to process variations of MOS transistors.SOLUTION: A first inverter includes a first PMOS transistor P1 and a first NMOS transistor N1. A correction circuit 10 has a second NMOS transistor N2 having a gate biased at a first predetermined potential and a drain connected to VDD and a second PMOS transistor P2 having a gate biased at a second predetermined potential and a drain connected to VSS, and has sources of both MOS transistors connected to each other and further the common source connected to an output of the first inverter. If a logic threshold voltage is set at VDD/2, the following relationship is satisfied for an input voltage of VDD/2: Rp1×Rn2/(Rp1+Rn2)=Rn1×Rp2/(Rn1+Rp2), where Rp1, Rp2, Rn1, Rn2 are values of resistance components of the first and second PMOS transistors P1,P2 and first and second NMOS transistors N1, N2, respectively.