Incremental synthesis
Daniel Brand,Anthony Drumm,Sandip Kundu,Prakash Narain +3 more
- 06 Nov 1994
pp 14-18
102
TL;DR: A method is described that solves the problem of small change in the input to logic synthesis by reusing gates from the old implementation, and restricting synthesis to the modified portions only.
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Abstract: A small change in the input to logic synthesis may cause a large change in the output implementation. This is undesirable if a designer has some investment in the old implementation and does not want it perturbed more than necessary. We describe a method that solves this problem by reusing gates from the old implementation, and restricting synthesis to the modified portions only.
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References
Automating the diagnosis and the rectification of design errors with PRIAM
Jean Christophe Madre,Olivier Coudert,J.-P. Billon +2 more
- 05 Nov 1989
TL;DR: The authors present the original extensions brought to PRIAM to automate both the diagnosis and the rectification of the design errors detected by this tool, implementing a novel approach to diagnosis based on Boolean equation solving.
115
Incremental synthesis for engineering changes
Y. Watanabe,Robert K. Brayton +1 more
- 14 Oct 1991
TL;DR: The problem of rectifying design incorrectness due to specification changes as well as design errors of VLSI circuits is formulated and a basic approach using logic synthesis techniques is presented, showing that the proposed approach always succeeds in the rectification of arbitrary combinational circuits.
50
Application of Boolean unification to combinational logic synthesis
Masahiro Fujita,Yutaka Tamiya,Y. Kukimoto,K.-C. Chen +3 more
- 11 Nov 1991
TL;DR: The authors present various applications of Boolean unification to combinational logic synthesis, including redesign, multilevel logic minimization, and minimization of Boolean relations.
43
Incremental Logic Synthesis through Gate Logic Structure Identification
Takao Shinsha,T. Kubo,Sakataya Yoshinori,J. Koshishita,K. Ishihara +4 more
- 02 Jul 1986
TL;DR: A gate logic structure identification and editing system has been developed with a corresponding gate matrix method as its core, which has greatly contributed to the increase in design efficiency of the very large computer series M68XH.
36
ACCORD : Automatic Catching and Correction of Logic Design Errors in Combinational Circuits
Pi-Yu Chung,I.N. Hajj +1 more
- 20 Sep 1992
TL;DR: It is shown that an erroneous czrcuzt can satzsfy ihe S‘LDE models, a solutzon as guaranteed, and the correctroil of miilfipie logac desagn errors zs also dzsciissed.
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