Patent
Incremental encoder frequency-dividing circuit
Hu Jianhua,Yunkuan Wang,Wang Xinbo,Wu Shaohong,Zheng Jun,Lu Hao,Su Tingting,Zhang Haojian,Yuan Yong +8 more
- 26 Apr 2017
3
TL;DR: In this article, an incremental encoder frequency-dividing circuit was proposed, which consists of a metastable state elimination circuit, a peak filtering circuit, quadruple frequency phase discrimination circuit and a counter circuit.
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Abstract: The invention discloses an incremental encoder frequency-dividing circuit. The circuit comprises a metastable state elimination circuit, a peak filtering circuit, a quadruple frequency phase discrimination circuit, a counter circuit and a pulse frequency-dividing circuit, the metastable state elimination circuit removes metastable state phenomena in A-phase pulse signals and B-phase pulse signals output by an incremental encoder and improves the stability of the circuit, the peak filtering circuit removes high-frequency interference in A-phase pulses and B-phase pulses output by the metastable state elimination circuit, the quadruple frequency phase discrimination circuit performs frequency quadruplication on the A-phase pulse signals and the B-phase pulse signals output by the peak filtering circuit and extracts direction signals so that the counter circuit can count the pulse subsequently, the counter circuit performs gain-loss counting according to the counting pulses and the direction signals output by the quadruple frequency phase discrimination circuit, and the pulse frequency-dividing circuit outputs the pulse signals after frequency dividing according to a counting value output by the counter circuit. By employing the circuit, arbitrary frequency-dividing output of the incremental encoder can be realized, and the precision and the anti-interference performance of the encoder can be effectively improved.
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Citations
Patent
Coded disc rotating speed calculation and fault detection method
Tian Kai,Zhang Ce,Wei Wei,Yang Gan,Yang Yufei,Zhao Jinpeng +5 more
- 24 Mar 2020
TL;DR: In this article, a coded disc rotating speed calculation and fault detection method is proposed for an AC motor speed regulation vector control system with adaptive filtering link in the detection process, which can improve the anti-interference performance, improve the rotating speed output precision through the coded disc signalfrequency multiplication processing, and improve the zero rotating speeds output quality through the zero-speed anti-shake processing.
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Jin Zhigang
- 20 May 2021
TL;DR: In this paper, the synchronization register and level conversion unit are connected by a high-voltage power supply in the dual power supplies, which provides electricity to the register for eliminating metastability.
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Sine signal and cosine signal processing method and system
Zhu Yunfei
- 07 Aug 2018
TL;DR: In this paper, a sine signal and cosine signal processing method for orthogonal square signals is presented. But the method is not suitable for counting the orthogonality of the received sine signals.
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Patent
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Yongli Li
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TL;DR: In this article, a method to realize arbitrary-number frequency dividing of servo driver and arbitrary number frequency divider based on field programmable gate array (FPGA) is presented.
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Patent
Implementation method for arbitrary fractional divider based on FPGA/CPLD
Tao Tao,Shen Jianguang,Mei Xuesong,Xu Muxun,Dongsheng Zhang,Peng Zhihui +5 more
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TL;DR: In this paper, an implementation method for an arbitrary fractional divider based on a FPGA/a CPLD is presented, which includes the following steps that a clock signal is input towards an Error register and a pulse output selector, wherein the frequency of the clock signal was fin.
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Patent
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