Improving Datapath Testability by Modifying Controller Specification
TL;DR: This paper proposes a method for specifying the control part in order to restore the testability of the datapath to a level close to the initial one, in other words its testability before connection.
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Abstract: A digital circuit includes two main parts: a controller and a datapath. After connection of these two parts, both are subject to a sharp fall in testability due to the lack of controllability and observability at the interface. In this paper, we propose a method for specifying the control part in order to restore the testability of the datapath to a level close to the initial one, in other words its testability before connection. This testability driven specification affects the next state logic as well as the decoder part of the controller but does not make use of any scan-based element. Based on the finite automata theory and on results of a testability analysis performed on the datapath, the proposed method entails very little area penalty.
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Citations
High-Level Test Synthesis: A Survey from Synthesis Process Flow Perspective
Selvaraj Ravi,M. Joseph +1 more
TL;DR: A detailed survey on recent developments in high-level test synthesis from a synthesis process flow perspective and a survey on controller synthesis techniques for testability are presented.
12
References
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Frank F. Hsu,Elizabeth M. Rudnick,Janak H. Patel +2 more
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TL;DR: Experimental results on several high-level synthesis benchmarks show that when this approach is used prior to logic synthesis, a shorter ATPG time, a smaller test set, and better fault coverage and ATPG efficiency are often achieved.
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Srivaths Ravi,Ganesh Lakshminarayana,Niraj K. Jha +2 more
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TL;DR: TAO exploits the algebra of regular expressions to provide a unified framework for handling a wide variety of circuits including application-specific integrated circuits, application- specific programmable processors, application -specific instruction processors, digital signal processors and microprocessors.
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Analyzing testability from behavioral to RT level
Marie-Lise Flottes,Ricardo Pires,Bruno Rouzeyre +2 more
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TL;DR: The testability analysis returns values that represent the relative difficulty for computing test data, whatever the level of description of a circuit is, from the behavioral level-initial specification-down to the Register Transfer Level-high level synthesis output.