Patent
Improved parity checking apparatus
Robert C. Nash,Peter A. Morrison +1 more
- 31 Mar 1989
2
TL;DR: In this paper, the authors present a parity checker for a synchronous bus, which is used with a diagnostic apparatus to record the occurrence of any parity error among devices attached to the bus.
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Abstract: Apparatus and methods for performing parity checking in an environment in which devices which perform parity checking (103) and those which do not (150) are connected to the same synchronous bus. The bus includes a parity enable line (113), which carries an parity enable signal indicating that the device transmitting data on the bus is a parity device which provides the parity of the data it transmits, a parity line (111), which carries the parity of the data being transmitted, and a parity error line (109) which carries a parity error signal indicating whether the receiving device detected a parity error. The data is transmitted in a first bus cycle, the parity enable signal and the parity are transmitted in the following bus cycle, and the receiving device transmits the parity error signal in the next bus cycle after that. The bus interface for each parity device includes a parity generator (327) and logic (519, 521, 523, 525, 509) which generates the parity and parity enable signals and receives the parity error signal when the parity device is transmitting and which receives the parity and parity enable signals and generates the parity error signal when the device is receiving. The apparatus is used with system diagnostic apparatus which records the occurrence of any parity error among devices attached to the bus.
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Citations
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References
Patent
Interface for use between a memory and components of a module switching apparatus
David L. Budde,David G. Carson,David B. Johnson,Doran Wilde +3 more
- 04 Jan 1982
TL;DR: In this paper, the memory bus is a packet-oriented bus, which is composed of processor buses (105) and corresponding control lines; and memory buses (107) with corresponding control line (108).
142
Patent
Circuit arrangement for telecommunication exchanges, especially telephone exchanges, with devices for securing the transmission of coded signals
Ulrich Dipl.-Ing. Heyland,Gerald Ing. Grad. Hoffmann +1 more
- 20 Sep 1982
TL;DR: In this article, a circuit arrangement for telecommunications exchanges, in particular telephone exchanges, was proposed, in which binary-coded information is transmitted by means of lines (C, L) which have a line wire for each code element, and in which transmitted information is both stored at the transmitting point (D) and fed to a comparator (V) and also re-stored after its transmission via the line.
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