Implementation of HfSiON gate dielectric for sub-60nm DRAM dual gate oxide with recess channel array transistor (RCAT) and tungsten gate

doi:10.1109/IEDM.2004.1419204

Proceedings Article10.1109/IEDM.2004.1419204

Implementation of HfSiON gate dielectric for sub-60nm DRAM dual gate oxide with recess channel array transistor (RCAT) and tungsten gate

Seong Geon Park, +11 more

- 13 Dec 2004

- pp 515-518

60

TL;DR: In this article, HfSiON gate dielectric is integrated for the first time in dual gate oxide of DRAM with recess channel arrary transistor (RCAT) and W/poly-Si gate for the development of sub-60nm DRAM technology.

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References

Proceedings Article•10.1109/VLSIT.2003.1221060

Fermi level pinning at the polySi/metal oxide interface

Chris Hobbs, +17 more

- 10 Jun 2003

TL;DR: In this article, the first time that Fermi pinning at the polySi/metal oxide interface causes high threshold voltages in MOSFET devices was reported. But the authors did not consider the effect of the interfacial Si-Hf and Si-O-Al bonds.

...read moreread less

154

Proceedings Article•10.1109/IEDM.2001.979519

COB stack DRAM cell technology beyond 100 nm technology node

Yongjik Park, +1 more

- 02 Dec 2001

TL;DR: In this article, the key technologies for future DRAM cells are investigated based on the COB stack cell for DRAM technology generations from 0.15 /spl mu/m node to 70 nm node.

...read moreread less

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