Proceedings Article10.1109/ISCAS.2016.7527389
Identifying systematic spatial failure patterns through wafer clustering
Mohamed Baker Alawieh,Fa Wang,Xin Li +2 more
- 22 May 2016
- pp 910-913
10
TL;DR: This paper proposes a novel methodology for detecting systematic spatial failure patterns at wafer level for yield learning by taking the testing results of a number of dies over different wafers, cluster all these wafer according to their failures, and eventually identify the underlying spatialFailure patterns.
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Abstract: In this paper, we propose a novel methodology for detecting systematic spatial failure patterns at wafer level for yield learning. Our proposed methodology takes the testing results (i.e., pass or fail) of a number of dies over different wafers, cluster all these wafers according to their failures, and eventually identify the underlying spatial failure patterns. Several novel machine learning algorithms, including singular value decomposition, hierarchical clustering, dictionary learning, etc., are developed in order to make the proposed methodology robust to random failures. The efficacy of our proposed approach is demonstrated by an industrial data set.
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Citations
Wafer Map Defect Patterns Classification using Deep Selective Learning
Mohamed Baker Alawieh,Duane S. Boning,David Z. Pan +2 more
- 20 Jul 2020
TL;DR: This paper proposes a novel methodology for wafer map defect pattern classification using deep selective learning that features an integrated reject option where the model chooses to abstain from predicting a class label when misclassification risk is high, providing a trade-off between prediction coverage and mis classification risk.
60
A Deep Learning Model for Identification of Defect Patterns in Semiconductor Wafer Map
Yang Yuan-Fu
- 06 May 2019
TL;DR: This paper employs convolutional neural networks (CNN) and extreme gradient boosting (XGBoost) for wafer map retrieval tasks and the defect pattern classification, and believes this is the first time accurate computational classification in such task has been reported achieving accuracy above 99%.
55
Identifying Wafer-Level Systematic Failure Patterns via Unsupervised Learning
TL;DR: A Pseudo-Boolean satisfiability solver is used to extract a minimal set of systematic failure patterns that explain all wafer-level spatial signatures that help process engineers identify the root causes of failures and accelerate yield learning.
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Novel method for detection of mixed-type defect patterns in wafer maps based on a single shot detector algorithm
TL;DR: In this article, a simple single shot detector was proposed to detect mixed-type defect patterns in which a single model was employed to detect the mixed pattern in a wafer bin map, which outperformed existing CNN-based methods and also provided defect location information.
27
Automated die inking: A pattern recognition-based approach
Constantinos Xanthopoulos,Peter Sarson,Heinz Reiter,Yiorgos Makris +3 more
- 01 Oct 2017
TL;DR: A novel pattern recognition methodology is introduced to learn and automatically generate the inking patterns from the failure maps, thus eliminating the need for human intervention during IC testing.
13
References
Determining the number of clusters/segments in hierarchical clustering/segmentation algorithms
Stan Salvador,Philip K. Chan +1 more
- 15 Nov 2004
TL;DR: This work proposes an efficient algorithm, the L method, that finds the "knee" in a '# of clusters vs. clustering evaluation metric' graph, using the knee is well-known, but is not a particularly well-understood method to determine the number of clusters.
Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits
TL;DR: This paper proposes a new technique, referred to as virtual probe (VP), to efficiently measure, characterize, and monitor spatially-correlated inter-die and/or intra-die variations in nanoscale manufacturing process, thereby reducing the cost of silicon characterization.
Virtual probe: a statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits
Xin Li,Rob R. Rutenbar,R.D. Blanton +2 more
- 02 Nov 2009
TL;DR: This paper proposes a new technique, referred to as virtual probe (VP), to efficiently measure, characterize and monitor both inter-die and spatially-correlated intra-die variations in nanoscale manufacturing process, thereby reducing the cost of silicon characterization.